Pub Date : 2020-12-14DOI: 10.1109/EDAPS50281.2020.9312897
Keeyoung Son, Subin Kim, Shinyoung Park, Hyunwook Park, Keunwoo Kim, Taein Shin, Minsu Kim, Kyungjune Son, Gapyeol Park, Seungtaek Jeong, Joungho Kim
In this paper, we firstly proposed a thermal transmission line (TTL) based embedded cooling structure for advanced thermal management of a next-generation high bandwidth memory (HBM) module. Thermal issues are critical to the development of HBM and 2.5D/3D ICs. The proposed TTL based embedded cooling structures can be one of the promising thermal management solutions for the 2.5D/3D ICs. The previous embedded cooling structures have thermal management limitations of the difficulties of cooling the internal heat of the 2.5D/3D ICs each layer. The proposed TTL transfers internal heat to the coolant to lowering junction temperature. Moreover, we checked the fabrication feasibility of the TTL with through silicon vias (TSVs). By using 3D electromagnetic (EM) and 3D fluent simulations, we analyzed the proposed TTL considering signal integrity (SI) and thermal integrity (TI). SI analysis showed the TTL does not contribute critical SI issues for HBM on-chip TSV channels. TI analysis provided the thermal management superiority of the TTL. As a result, it showed the improvement of TI of HBM module decreased HBM junction temperature by 4.789°C compared to the previous embedded cooling structure.
{"title":"Design and Analysis of Thermal Transmission Line based Embedded Cooling Structures for High Bandwidth Memory Module and 2.5D/3D ICs","authors":"Keeyoung Son, Subin Kim, Shinyoung Park, Hyunwook Park, Keunwoo Kim, Taein Shin, Minsu Kim, Kyungjune Son, Gapyeol Park, Seungtaek Jeong, Joungho Kim","doi":"10.1109/EDAPS50281.2020.9312897","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312897","url":null,"abstract":"In this paper, we firstly proposed a thermal transmission line (TTL) based embedded cooling structure for advanced thermal management of a next-generation high bandwidth memory (HBM) module. Thermal issues are critical to the development of HBM and 2.5D/3D ICs. The proposed TTL based embedded cooling structures can be one of the promising thermal management solutions for the 2.5D/3D ICs. The previous embedded cooling structures have thermal management limitations of the difficulties of cooling the internal heat of the 2.5D/3D ICs each layer. The proposed TTL transfers internal heat to the coolant to lowering junction temperature. Moreover, we checked the fabrication feasibility of the TTL with through silicon vias (TSVs). By using 3D electromagnetic (EM) and 3D fluent simulations, we analyzed the proposed TTL considering signal integrity (SI) and thermal integrity (TI). SI analysis showed the TTL does not contribute critical SI issues for HBM on-chip TSV channels. TI analysis provided the thermal management superiority of the TTL. As a result, it showed the improvement of TI of HBM module decreased HBM junction temperature by 4.789°C compared to the previous embedded cooling structure.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125316938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-14DOI: 10.1109/EDAPS50281.2020.9312916
Minh Quach, N. Devnani, Mark Hinton, R. Kaw
Intra-pair skew typically length compensation by extra trace length with several bends. These bends cause a speed-up in signal transmission. This study addresses the speed-up correction for strip-lines with any-angle-bends as find in the package.
{"title":"Sub-picosecond Skew Matching","authors":"Minh Quach, N. Devnani, Mark Hinton, R. Kaw","doi":"10.1109/EDAPS50281.2020.9312916","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312916","url":null,"abstract":"Intra-pair skew typically length compensation by extra trace length with several bends. These bends cause a speed-up in signal transmission. This study addresses the speed-up correction for strip-lines with any-angle-bends as find in the package.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114508663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-14DOI: 10.1109/EDAPS50281.2020.9312909
Gapyeol Park, Hyunwook Park, Daehwan Lho, Junyong Park, Kyungjune Son, Seongguk Kim, Taein Shin, Keeyoung Son, Joonsang Park, Joungho Kim, Junho Lee, Seong-Joon Choi
In this paper, we propose the design of a HDMI 2.1 connector for 8K TV considering signal integrity (SI). Also, we firstly measure the proposed HDMI 2.1 connector. To achieve the high data rate, connector should be designed by considering not only mechanical characteristics but also electrical characteristics. We design the HDMI 2.1 connector considering SI including characteristic impedance, differential insertion loss and attenuation to crosstalk ratio (ACR). We revise the structure of metal pins and dielectric materials for improving the SI performances. Proposed HDMI 2.1 connector was verified by time-domain and frequency domain simulation using the 3D electromagnetic (EM) simulator. Proposed HDMI 2.1 connector showed improve SI performance than previous connector. Also, proposed connector was verified through measurement. With the proposed HDMI design, it shows better SI characteristics at the 24 Gbps which is expected to next generation HDMI connector’s data rate.
{"title":"Design and Measurement of a HDMI 2.1 Connector for 8K TV considering Signal Integrity","authors":"Gapyeol Park, Hyunwook Park, Daehwan Lho, Junyong Park, Kyungjune Son, Seongguk Kim, Taein Shin, Keeyoung Son, Joonsang Park, Joungho Kim, Junho Lee, Seong-Joon Choi","doi":"10.1109/EDAPS50281.2020.9312909","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312909","url":null,"abstract":"In this paper, we propose the design of a HDMI 2.1 connector for 8K TV considering signal integrity (SI). Also, we firstly measure the proposed HDMI 2.1 connector. To achieve the high data rate, connector should be designed by considering not only mechanical characteristics but also electrical characteristics. We design the HDMI 2.1 connector considering SI including characteristic impedance, differential insertion loss and attenuation to crosstalk ratio (ACR). We revise the structure of metal pins and dielectric materials for improving the SI performances. Proposed HDMI 2.1 connector was verified by time-domain and frequency domain simulation using the 3D electromagnetic (EM) simulator. Proposed HDMI 2.1 connector showed improve SI performance than previous connector. Also, proposed connector was verified through measurement. With the proposed HDMI design, it shows better SI characteristics at the 24 Gbps which is expected to next generation HDMI connector’s data rate.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122167921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-14DOI: 10.1109/EDAPS50281.2020.9312896
L. Hwang, C. Wang, Ming-Yuan Huang, Hung-Chih Lin, Chien-Chang Huang
Some suggested that four-port single-ended scattering S-parameters (simulated or measured) be converted and used to represent mixed-mode S-parameters; the approach we label here as "SE-matrix converted," or simply "SE-conv." SE-conv is often preferred, since the mixed-mode signal sources and probes are not readily or easily available. To employ the SE-conv formulation, the two lines have to be loosely coupled. This restriction curtails in differential bias in the mixed-mode feeding the considerations of 1) existence of virtual ground, and 2) defect ground that may be present in the system ground. First, when the virtual ground existing between lines is not considered (due to loosely coupling assumption), detailed capacitive referencing (line held at +V to virtual ground, and virtual ground to other line held at –V in differential feed) is thus ignored. Three CPL configurations were employed here to investigate the impacts of close coupling, including the effect of virtual ground and its associated capacitive referencing. The progress is reported in this paper. Secondly, effects of ground defect is directly picked up by SE feeding, while in mixed-mode feeding, the effect is somehow reduced (or resisted) by the virtual ground. The investigation on this issue is in progress, and we will report the results later. Keywords— CPL (Coupled Line), Single-ended and mixed-mode feeds, Differential & common mode stimuli, Coupled line, Stripline, Microstrip, and Co-planar ground, Virtual ground, Defect ground, Scattering parameters, Network analyzer
{"title":"Investigation of Sideway Coupling Effects of Virtual Ground in Three Types of Coupled Line with Mixed-mode Stimuli","authors":"L. Hwang, C. Wang, Ming-Yuan Huang, Hung-Chih Lin, Chien-Chang Huang","doi":"10.1109/EDAPS50281.2020.9312896","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312896","url":null,"abstract":"Some suggested that four-port single-ended scattering S-parameters (simulated or measured) be converted and used to represent mixed-mode S-parameters; the approach we label here as \"SE-matrix converted,\" or simply \"SE-conv.\" SE-conv is often preferred, since the mixed-mode signal sources and probes are not readily or easily available. To employ the SE-conv formulation, the two lines have to be loosely coupled. This restriction curtails in differential bias in the mixed-mode feeding the considerations of 1) existence of virtual ground, and 2) defect ground that may be present in the system ground. First, when the virtual ground existing between lines is not considered (due to loosely coupling assumption), detailed capacitive referencing (line held at +V to virtual ground, and virtual ground to other line held at –V in differential feed) is thus ignored. Three CPL configurations were employed here to investigate the impacts of close coupling, including the effect of virtual ground and its associated capacitive referencing. The progress is reported in this paper. Secondly, effects of ground defect is directly picked up by SE feeding, while in mixed-mode feeding, the effect is somehow reduced (or resisted) by the virtual ground. The investigation on this issue is in progress, and we will report the results later. Keywords— CPL (Coupled Line), Single-ended and mixed-mode feeds, Differential & common mode stimuli, Coupled line, Stripline, Microstrip, and Co-planar ground, Virtual ground, Defect ground, Scattering parameters, Network analyzer","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117284191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-14DOI: 10.1109/EDAPS50281.2020.9312894
Venkatesh Avula, B. Bhattacharyya, V. Smet, Y. Joshi, M. Swaminathan
Heterogeneous integration of power delivery circuits provides for a system-scaling opportunity in the post-Moore era. However, the integrated voltage regulator (IVR) poses complex design challenges. In this paper, the fundamental challenges and benefits, arising from the IVR-based power delivery system, in the electrical, thermal, and electromagnetics domains are analyzed. To verify the analysis, a comparison study of the regulator architectures with and without heterogeneous integration is considered. Also, metrics for the IVR design space are provided as measures to address its integration complexity and figure-of-merit.
{"title":"Multiphysics challenges with Heterogeneous Integrated Voltage Regulator based Power Delivery Architectures","authors":"Venkatesh Avula, B. Bhattacharyya, V. Smet, Y. Joshi, M. Swaminathan","doi":"10.1109/EDAPS50281.2020.9312894","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312894","url":null,"abstract":"Heterogeneous integration of power delivery circuits provides for a system-scaling opportunity in the post-Moore era. However, the integrated voltage regulator (IVR) poses complex design challenges. In this paper, the fundamental challenges and benefits, arising from the IVR-based power delivery system, in the electrical, thermal, and electromagnetics domains are analyzed. To verify the analysis, a comparison study of the regulator architectures with and without heterogeneous integration is considered. Also, metrics for the IVR design space are provided as measures to address its integration complexity and figure-of-merit.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114366969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-14DOI: 10.1109/EDAPS50281.2020.9312919
M. A. Dolatsara, Huan Yu, J. Hejase, Wiren Dale Becker, M. Swaminathan
Designing CTLE of high-speed channels can be complicated and time consuming. To alleviate this issue, this paper investigates the invertible neural networks (INNs) for inverse design of the CTLE. In this approach, a desired eye height and eye width is given, and the algorithm finds the corresponding peaking frequency and gain value of the CTLE. INN is a special type of neural networks that can be traversed in both forward and reverse directions. An advantage of this network is producing distribution of the input variables based on the desired output. This feature enables the algorithm to provide multiple solutions when a multi-modal distribution is produced. Thus, the user can choose the appropriate solution based on other constraints. A numerical example for inverse design of CTLE of a SerDes channel is provided, which results in moderate accuracy. However, other variations of the example show that the accuracy is case dependent which implies improvements on the algorithm is needed.
{"title":"Invertible Neural Networks for Inverse Design of CTLE in High-speed Channels","authors":"M. A. Dolatsara, Huan Yu, J. Hejase, Wiren Dale Becker, M. Swaminathan","doi":"10.1109/EDAPS50281.2020.9312919","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312919","url":null,"abstract":"Designing CTLE of high-speed channels can be complicated and time consuming. To alleviate this issue, this paper investigates the invertible neural networks (INNs) for inverse design of the CTLE. In this approach, a desired eye height and eye width is given, and the algorithm finds the corresponding peaking frequency and gain value of the CTLE. INN is a special type of neural networks that can be traversed in both forward and reverse directions. An advantage of this network is producing distribution of the input variables based on the desired output. This feature enables the algorithm to provide multiple solutions when a multi-modal distribution is produced. Thus, the user can choose the appropriate solution based on other constraints. A numerical example for inverse design of CTLE of a SerDes channel is provided, which results in moderate accuracy. However, other variations of the example show that the accuracy is case dependent which implies improvements on the algorithm is needed.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127675922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-14DOI: 10.1109/EDAPS50281.2020.9312913
S. Govindan, K. Bharath, S. Venkataraman, D. Gope
A simple and accurate method is proposed to model the Vccin feedthrough noise in microprocessors with Fully Integrated Voltage Regulators (FIVR). The method is based on averaged state-space models of FIVR and the Vccin network derived from the pole-residue models.
{"title":"A Large-Signal Method for Modeling Vccin feedthrough Noise in Microprocessors with Fully Integrated Voltage Regulators","authors":"S. Govindan, K. Bharath, S. Venkataraman, D. Gope","doi":"10.1109/EDAPS50281.2020.9312913","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312913","url":null,"abstract":"A simple and accurate method is proposed to model the Vccin feedthrough noise in microprocessors with Fully Integrated Voltage Regulators (FIVR). The method is based on averaged state-space models of FIVR and the Vccin network derived from the pole-residue models.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130245093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-14DOI: 10.1109/EDAPS50281.2020.9312889
Ming-Ming Li, Hong-li Peng, Ya-Bin Li, Chen-Chen Chen-Chen, Qingmian Wan
A novel structure of bondwire and microstrip lines for Chip-to-Chip inter-connection up to 130GHz is firstly pre-sented in this paper. Its realization is based on PCB heterogeneous integration process. In order to reduce its high inserted loss which mainly caused of high inductance of the bondwire, the microstrip line of the structure is then optimized. Simulated results show that the minimum insertion loss of 1.0 dB for the structure can be achieved, with the bandwidth more than 35 GHz in bands of 100-135 GHz.
{"title":"A Novel Structure of Bondwire and Microstrip Lines for Chip-to-Chip Inter-Connection Up to 130GHz","authors":"Ming-Ming Li, Hong-li Peng, Ya-Bin Li, Chen-Chen Chen-Chen, Qingmian Wan","doi":"10.1109/EDAPS50281.2020.9312889","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312889","url":null,"abstract":"A novel structure of bondwire and microstrip lines for Chip-to-Chip inter-connection up to 130GHz is firstly pre-sented in this paper. Its realization is based on PCB heterogeneous integration process. In order to reduce its high inserted loss which mainly caused of high inductance of the bondwire, the microstrip line of the structure is then optimized. Simulated results show that the minimum insertion loss of 1.0 dB for the structure can be achieved, with the bandwidth more than 35 GHz in bands of 100-135 GHz.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132626049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A miniaturized and high frequency response 35 GHz frequency modulated continuous wave (FMCW) radar system is presented for short range target detections. The system mainly consists of two antennas, a single chip transceiver and a signal processor. Thanks to our design and integrated techniques, high performance of the system is achieved and also verified by experimental results using our fabricated prototype. Our results show that the detection accuracy of 0.2m can be achieved for 15cm *15cm metal targets within detection distance of 12m, along with the radar system total size of 29mm in diameter, which agrees well with our design.
{"title":"A Miniaturized and High Frequency Response 35GHz FMCW Radar for Short Range Target Detections","authors":"Ya-Bin Li, Hong-li Peng, Ming-Ming Li, Weihao Li, Chen Chen, Qingmian Wan","doi":"10.1109/EDAPS50281.2020.9312915","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312915","url":null,"abstract":"A miniaturized and high frequency response 35 GHz frequency modulated continuous wave (FMCW) radar system is presented for short range target detections. The system mainly consists of two antennas, a single chip transceiver and a signal processor. Thanks to our design and integrated techniques, high performance of the system is achieved and also verified by experimental results using our fabricated prototype. Our results show that the detection accuracy of 0.2m can be achieved for 15cm *15cm metal targets within detection distance of 12m, along with the radar system total size of 29mm in diameter, which agrees well with our design.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127630680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-14DOI: 10.1109/EDAPS50281.2020.9312910
Vinod Arjun Huddar
A simplified methodology for On-Die clock tree Power Supply Induced Jitter (PSIJ) analysis is put forth. The approach estimates jitter induced on a clock output (CK) without introducing significant error while significantly reducing simulation times. Approach relies on analysis of various transfer functions of on-die linear regulators. The accuracy of this simplified approach is highly dependent on on-die linear regulator design.
{"title":"On Die Clock Tree PSIJ Simplified","authors":"Vinod Arjun Huddar","doi":"10.1109/EDAPS50281.2020.9312910","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312910","url":null,"abstract":"A simplified methodology for On-Die clock tree Power Supply Induced Jitter (PSIJ) analysis is put forth. The approach estimates jitter induced on a clock output (CK) without introducing significant error while significantly reducing simulation times. Approach relies on analysis of various transfer functions of on-die linear regulators. The accuracy of this simplified approach is highly dependent on on-die linear regulator design.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133837116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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