Process development to enable die sorting and 3D IC stacking

Abstract

3D stacking is a relative new technology and presents numerous challenges that need to be addressed for enabling high volume manufacturing. Yield and reliability are strongly affected by typical 3D processes: TSV, wafer thinning, stacking. For 3D stacking the die thickness is typically 50um with some exceptions for Interposer applications (typically 100um thick). This work describes some of the key challenges that need to be addressed to enable stacking of thick and thin dies. In this paper we report on process steps and equipment optimization that are required to enable 3D stacks. We focus on two main processes: die sorting (or die pick and place) and die stacking. For die sorting we report on the parameters considered to select the right ‘eject’ and ‘pick up’ tools and present considerations for process optimizations. For die stacking we report about temperature control during stacking and about the effects that foreign particles may have on stacking alignment.