Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507164
C. Selvanayagam, Rathin Mandal
With the increased popularity of ultra-portable electronics such as laptops, microprocessor manufacturers have had to move away from the conventional and highly reliable pin-grid array (PGA) packages and towards ball-grid array (BGA) packages for this market segment due to thickness restrictions. This shift brings with it some reliability concerns. In addition, to shrink the form factor and improve electrical performance further, standard-core substrates are being swapped for thin-core and coreless variations. This work evaluates BGA performance of flip-chip packages with coreless substrates through finite element analysis (FEA) simulation. A three-dimensional quarter-model of a package with no heat spreader on coreless substrate with mixed BGA pitch was used so the location of expected failure can be simulated more accurately. This work then proposes a methodology for improving BGA reliability of coreless packages. Taking into account the behavior of coreless BGA packages, it is proposed that one possible method to improve BGA life in these packages would be to convert the few critical joints to dummy (power/ground plane) joints such that failure of the critical die corner joints does not result in failure of the part. This can be implemented by a design rule that stipulates the replacement of critical die corner joints with dummy joints in coreless substrates. We determined expected percentage improvement in BGA life with the implementation of such a design rule using FEA simulations and Miner's rule: for the BGA layout assumed here, results indicate that 130% improvement in BGA life is possible when five solder joints at the die corner are replaced with dummy joints. This work will be useful for robust design of solder joints in BGA packages with coreless substrates.
{"title":"Simulation approach to improving BGA reliability on coreless packages","authors":"C. Selvanayagam, Rathin Mandal","doi":"10.1109/EPTC.2012.6507164","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507164","url":null,"abstract":"With the increased popularity of ultra-portable electronics such as laptops, microprocessor manufacturers have had to move away from the conventional and highly reliable pin-grid array (PGA) packages and towards ball-grid array (BGA) packages for this market segment due to thickness restrictions. This shift brings with it some reliability concerns. In addition, to shrink the form factor and improve electrical performance further, standard-core substrates are being swapped for thin-core and coreless variations. This work evaluates BGA performance of flip-chip packages with coreless substrates through finite element analysis (FEA) simulation. A three-dimensional quarter-model of a package with no heat spreader on coreless substrate with mixed BGA pitch was used so the location of expected failure can be simulated more accurately. This work then proposes a methodology for improving BGA reliability of coreless packages. Taking into account the behavior of coreless BGA packages, it is proposed that one possible method to improve BGA life in these packages would be to convert the few critical joints to dummy (power/ground plane) joints such that failure of the critical die corner joints does not result in failure of the part. This can be implemented by a design rule that stipulates the replacement of critical die corner joints with dummy joints in coreless substrates. We determined expected percentage improvement in BGA life with the implementation of such a design rule using FEA simulations and Miner's rule: for the BGA layout assumed here, results indicate that 130% improvement in BGA life is possible when five solder joints at the die corner are replaced with dummy joints. This work will be useful for robust design of solder joints in BGA packages with coreless substrates.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124849687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507154
Y. B. Kar, Noor Azrma Tahk, Foong Chee Seng, L. H. Yang, R. Vithyacharan, T. Yong
This paper discusses the evaluation and characterizations of the cleaning the organic residues on Flip Chip Ceramic Ball Grid Array (FCCBGA) package. Flux used for Control Collapse Chip Connection (C4) die attachment during assemblies could remain on the die surface as organic residues, thus affecting the integrated circuit performance. Therefore, the effect of implementation flux-cleaning process on the die cleanliness was evaluated. Design of Experiments (DOE) for cleaning chemical parameters using water-based solvents was carried out to investigate the flux-cleaning efficiency. The response for the experiments conducted was die surface cleanliness. The presence and levels of contaminations would be analyzed and characterized using Scanning Electron Microscope (SEM), Fourier Transform Infrared Spectroscopy (FTIR) and Ion chromatography (IC). The optimization process required the integration between mechanical and chemical parameters. Chemical cleaning parameters optimization was aided with Micro Phase Cleaning (MPC) as solvent. Wash temperature and solvent concentration were varied to find the optimal cleaning. Whilst for mechanical parameters, washing pressure, and nozzle orientation are the expected parameters that would give impact to the cleaning process. From the experiments, the cleaning process is optimized with 3% of MPC solvent added into the pure DI water with longer wash exposure time 0.3 m/mm at 10 Psi with 75°C. The optimization result is proven with thermal cycle testing where no delammation or voids are detected even after 2500x.
{"title":"Flux residue cleaning process optimization effect on Flip Chip Ball Grid Array reliability","authors":"Y. B. Kar, Noor Azrma Tahk, Foong Chee Seng, L. H. Yang, R. Vithyacharan, T. Yong","doi":"10.1109/EPTC.2012.6507154","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507154","url":null,"abstract":"This paper discusses the evaluation and characterizations of the cleaning the organic residues on Flip Chip Ceramic Ball Grid Array (FCCBGA) package. Flux used for Control Collapse Chip Connection (C4) die attachment during assemblies could remain on the die surface as organic residues, thus affecting the integrated circuit performance. Therefore, the effect of implementation flux-cleaning process on the die cleanliness was evaluated. Design of Experiments (DOE) for cleaning chemical parameters using water-based solvents was carried out to investigate the flux-cleaning efficiency. The response for the experiments conducted was die surface cleanliness. The presence and levels of contaminations would be analyzed and characterized using Scanning Electron Microscope (SEM), Fourier Transform Infrared Spectroscopy (FTIR) and Ion chromatography (IC). The optimization process required the integration between mechanical and chemical parameters. Chemical cleaning parameters optimization was aided with Micro Phase Cleaning (MPC) as solvent. Wash temperature and solvent concentration were varied to find the optimal cleaning. Whilst for mechanical parameters, washing pressure, and nozzle orientation are the expected parameters that would give impact to the cleaning process. From the experiments, the cleaning process is optimized with 3% of MPC solvent added into the pure DI water with longer wash exposure time 0.3 m/mm at 10 Psi with 75°C. The optimization result is proven with thermal cycle testing where no delammation or voids are detected even after 2500x.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114916893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507088
O. Ho, C. Wee
Ultrasonic vibration behavior of wire bonding capillaries was studied with laser vibrometer at free air and bonding stage. Vibration displacement was measured at transducer, capillary body and capillary tip at the interval of 1mm with Laser Doppler Vibrometer (LDV). This study focus on five different capillaries with same tip design, namely of three standard design capillaries with different main taper angle (MTA) and two special body cut capillaries. Wire bonding responses and capillary vibration behaviors was studied under different conditions. First, they were compared under same bond power setting. Second, each capillary were calibrated with same tip vibration displacement at free air by changing the bond power. Third same ball shear response was calibrated by adjusting bond power. In general, it is observed that when the vibration nodal position is farther from capillary tip (or higher), larger vibration displacement is generated at capillary tip. For special cut capillaries, capillary B with higher vibration nodal position than capillary A has shown larger tip vibration displacement, and it requires lesser bond power to produce same ball shear response. As for standard design capillary, with larger MTA, the vibration nodal position is lower and smaller tip vibration. Although with smaller tip vibration, it has shown better bonding results. The percentage of tip vibration displacement reduction for larger MTA capillary is lesser, and it requires lesser bond power to produce same ball shear response. From this study, we have understood that special cut capillary have different working principles than standard design capillary. The results of this study have demonstrated an in-depth understanding of the ultrasonic vibration behavior of different bonding capillary body design in both free air and bonding stage; and the impact on the wire bonding responses. Subsequently, this understanding is a step forward to develop the capillary material and design guideline.
{"title":"Wire bonding capillary vibration behaviour through Laser Doppler Vibrometry & its effects on wire bonding responses","authors":"O. Ho, C. Wee","doi":"10.1109/EPTC.2012.6507088","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507088","url":null,"abstract":"Ultrasonic vibration behavior of wire bonding capillaries was studied with laser vibrometer at free air and bonding stage. Vibration displacement was measured at transducer, capillary body and capillary tip at the interval of 1mm with Laser Doppler Vibrometer (LDV). This study focus on five different capillaries with same tip design, namely of three standard design capillaries with different main taper angle (MTA) and two special body cut capillaries. Wire bonding responses and capillary vibration behaviors was studied under different conditions. First, they were compared under same bond power setting. Second, each capillary were calibrated with same tip vibration displacement at free air by changing the bond power. Third same ball shear response was calibrated by adjusting bond power. In general, it is observed that when the vibration nodal position is farther from capillary tip (or higher), larger vibration displacement is generated at capillary tip. For special cut capillaries, capillary B with higher vibration nodal position than capillary A has shown larger tip vibration displacement, and it requires lesser bond power to produce same ball shear response. As for standard design capillary, with larger MTA, the vibration nodal position is lower and smaller tip vibration. Although with smaller tip vibration, it has shown better bonding results. The percentage of tip vibration displacement reduction for larger MTA capillary is lesser, and it requires lesser bond power to produce same ball shear response. From this study, we have understood that special cut capillary have different working principles than standard design capillary. The results of this study have demonstrated an in-depth understanding of the ultrasonic vibration behavior of different bonding capillary body design in both free air and bonding stage; and the impact on the wire bonding responses. Subsequently, this understanding is a step forward to develop the capillary material and design guideline.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116424673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507098
A. L. Manna, R. Daily, G. Capuz, J. de Vos, K. Rebibis, L. Bogaerts, A. Miller, E. Beyne
3D stacking is a relative new technology and presents numerous challenges that need to be addressed for enabling high volume manufacturing. Yield and reliability are strongly affected by typical 3D processes: TSV, wafer thinning, stacking. For 3D stacking the die thickness is typically 50um with some exceptions for Interposer applications (typically 100um thick). This work describes some of the key challenges that need to be addressed to enable stacking of thick and thin dies. In this paper we report on process steps and equipment optimization that are required to enable 3D stacks. We focus on two main processes: die sorting (or die pick and place) and die stacking. For die sorting we report on the parameters considered to select the right ‘eject’ and ‘pick up’ tools and present considerations for process optimizations. For die stacking we report about temperature control during stacking and about the effects that foreign particles may have on stacking alignment.
{"title":"Process development to enable die sorting and 3D IC stacking","authors":"A. L. Manna, R. Daily, G. Capuz, J. de Vos, K. Rebibis, L. Bogaerts, A. Miller, E. Beyne","doi":"10.1109/EPTC.2012.6507098","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507098","url":null,"abstract":"3D stacking is a relative new technology and presents numerous challenges that need to be addressed for enabling high volume manufacturing. Yield and reliability are strongly affected by typical 3D processes: TSV, wafer thinning, stacking. For 3D stacking the die thickness is typically 50um with some exceptions for Interposer applications (typically 100um thick). This work describes some of the key challenges that need to be addressed to enable stacking of thick and thin dies. In this paper we report on process steps and equipment optimization that are required to enable 3D stacks. We focus on two main processes: die sorting (or die pick and place) and die stacking. For die sorting we report on the parameters considered to select the right ‘eject’ and ‘pick up’ tools and present considerations for process optimizations. For die stacking we report about temperature control during stacking and about the effects that foreign particles may have on stacking alignment.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114258495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507058
J. R. Cubillo, R. Weerasekera, G. Katti, R. Patti
Driven by the internet bandwidth ever increasing demand, modern logic integrated circuits (IC) need to cope for logic to memory (DRAM) data throughput above the Terabit per seconds (Tbps) range [1]. Such logic to DRAM interface is affected by the memory wall bottlenecks like: logic operating at much higher throughput and lower latency than DRAM individual modules, and with limited pin count capability organic packaging solutions leading to system architecture using serialization techniques (at the expense of power dissipation and additional circuit latency). Those bottlenecks cannot be addressed individually and need a more global approach with new packaging solutions, new devices and overall enhanced architecture. We will present in this study a silicon packaging solution that can be optimized to achieve the highest possible throughput between logic and DRAM. First, we will explain the concept of high performance silicon carrier with its key specifications as well as the metrics to be analyzed, and then we will provide design rules guidelines and a methodology to optimize such silicon carrier for the highest possible throughput performance.
{"title":"Through-Silicon Interposer (TSI) co-design optimization for high performance systems","authors":"J. R. Cubillo, R. Weerasekera, G. Katti, R. Patti","doi":"10.1109/EPTC.2012.6507058","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507058","url":null,"abstract":"Driven by the internet bandwidth ever increasing demand, modern logic integrated circuits (IC) need to cope for logic to memory (DRAM) data throughput above the Terabit per seconds (Tbps) range [1]. Such logic to DRAM interface is affected by the memory wall bottlenecks like: logic operating at much higher throughput and lower latency than DRAM individual modules, and with limited pin count capability organic packaging solutions leading to system architecture using serialization techniques (at the expense of power dissipation and additional circuit latency). Those bottlenecks cannot be addressed individually and need a more global approach with new packaging solutions, new devices and overall enhanced architecture. We will present in this study a silicon packaging solution that can be optimized to achieve the highest possible throughput between logic and DRAM. First, we will explain the concept of high performance silicon carrier with its key specifications as well as the metrics to be analyzed, and then we will provide design rules guidelines and a methodology to optimize such silicon carrier for the highest possible throughput performance.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114608439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507186
N. Jurgensen, Q. Huynh, G. Engelmann, H. Ngo, O. Ehrmann, K.-D. Lang, A. Uhlig, T. Dretschkow, D. Rohde, O. Worm, C. Jager
For the electrochemical filling of through silicon vias (TSVs) the geometry of these vias as well as their quantity on the wafer have a severe influence on the electrochemical process parameters, in particular on the current process time profile. So the electrochemical deposition (ECD) current was investigated in dependence of the filling progress, the height-to-depth aspect ratio, and the quantity of high aspect ratio vias on the wafer. The same applies to the number of plating steps at constant current, their length, and the total process time. Valuable insights for the design of via filing recipes could be deduce thereof.
{"title":"Copper filling of TSVs for interposer applications","authors":"N. Jurgensen, Q. Huynh, G. Engelmann, H. Ngo, O. Ehrmann, K.-D. Lang, A. Uhlig, T. Dretschkow, D. Rohde, O. Worm, C. Jager","doi":"10.1109/EPTC.2012.6507186","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507186","url":null,"abstract":"For the electrochemical filling of through silicon vias (TSVs) the geometry of these vias as well as their quantity on the wafer have a severe influence on the electrochemical process parameters, in particular on the current process time profile. So the electrochemical deposition (ECD) current was investigated in dependence of the filling progress, the height-to-depth aspect ratio, and the quantity of high aspect ratio vias on the wafer. The same applies to the number of plating steps at constant current, their length, and the total process time. Valuable insights for the design of via filing recipes could be deduce thereof.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128562509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507048
L. Ruiqi, T. E. Lim, Tan Kwan Ling, M. Narducci, S. Tao, Cheng Ming-Yuan
Traumatic brain injury (TBI) can be worsen by the secondary brain injury which will the major prognostic factor for the patient condition. The major parameters for monitoring the TBI are the intracranial pressure, partial brain oxygen level and the brain temperature. This leads to the development of an integrated intracranial microsystem which effectively monitored the condition of the TBI patient. This paper will present the biocompatible packaging and its in-vitro result for the microsytem.
{"title":"Biocompatible packaging development for an intracranial microsystem","authors":"L. Ruiqi, T. E. Lim, Tan Kwan Ling, M. Narducci, S. Tao, Cheng Ming-Yuan","doi":"10.1109/EPTC.2012.6507048","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507048","url":null,"abstract":"Traumatic brain injury (TBI) can be worsen by the secondary brain injury which will the major prognostic factor for the patient condition. The major parameters for monitoring the TBI are the intracranial pressure, partial brain oxygen level and the brain temperature. This leads to the development of an integrated intracranial microsystem which effectively monitored the condition of the TBI patient. This paper will present the biocompatible packaging and its in-vitro result for the microsytem.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124745769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507081
Takayuki Kobayashi, S. Terashima, Masamoto Tanaka
Drop impact property after the solder joints were subjected to thermomechanical fatigue stresses were investigated. The solder compositions were SAC105 (Sn-1Ag-0.5Cu), SAC305 (Sn-3Ag-0.5Cu), and LF210N (Sn-2Ag-1Cu-0.05Ni) and the temperature range of the thermomechanical fatigue was from −45 degree of centigrade to +125 degree of centigrade. After 200 cycles of thermomechanical treatment, the drop property of SAC105 and SAC305 is almost the same low level whereas the drop property of LF210N keeps as-reflowed level. Microstructural observation revealed the difference of the fracture mode in these three solder compositions.
{"title":"Effect of thermomechanical fatigue on drop impact properties of Sn-Ag-Cu lead-free solder joints","authors":"Takayuki Kobayashi, S. Terashima, Masamoto Tanaka","doi":"10.1109/EPTC.2012.6507081","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507081","url":null,"abstract":"Drop impact property after the solder joints were subjected to thermomechanical fatigue stresses were investigated. The solder compositions were SAC105 (Sn-1Ag-0.5Cu), SAC305 (Sn-3Ag-0.5Cu), and LF210N (Sn-2Ag-1Cu-0.05Ni) and the temperature range of the thermomechanical fatigue was from −45 degree of centigrade to +125 degree of centigrade. After 200 cycles of thermomechanical treatment, the drop property of SAC105 and SAC305 is almost the same low level whereas the drop property of LF210N keeps as-reflowed level. Microstructural observation revealed the difference of the fracture mode in these three solder compositions.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114612523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507123
L. Peng, L. Zhang, H.Y. Li, G. Lo, C. Tan
In this paper, the mechanical properties of wafer-level high density Cu-Cu bonding are analyzed. The fabrication flow is optimized based on surface cleanliness, wafer uniformity, W2W alignment accuracy and oxide recess for successful bonding. Post- bonding characterizations include shear test and failure analysis to identify the mechanical strength and failure mechanisms. It is found that failures at Cu-Cu bonding interface are largely attributed to wafer non-uniformity.
{"title":"Mechanical characterization of wafer level bump-less Cu-Cu bonding","authors":"L. Peng, L. Zhang, H.Y. Li, G. Lo, C. Tan","doi":"10.1109/EPTC.2012.6507123","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507123","url":null,"abstract":"In this paper, the mechanical properties of wafer-level high density Cu-Cu bonding are analyzed. The fabrication flow is optimized based on surface cleanliness, wafer uniformity, W2W alignment accuracy and oxide recess for successful bonding. Post- bonding characterizations include shear test and failure analysis to identify the mechanical strength and failure mechanisms. It is found that failures at Cu-Cu bonding interface are largely attributed to wafer non-uniformity.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"27 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113978999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/EPTC.2012.6507102
P. Coudrain, J. Colonna, C. Aumont, G. Garnier, P. Chausse, R. Segaud, K. Vial, A. Jouve, T. Mourier, T. Magis, P. Besson, L. Gabette, C. Brunet-Manquat, N. Allouti, C. Laviron, S. Chéramy, E. Saugier, J. Pruvost, A. Farcy, N. Hotellier
This paper presents the prototype of a 3D circuit with Wide I/O interconnects in a 65nm CMOS node, assembled in a face-to-back integration and reported on a BGA. The process technology carried out for the realization of the bottom die will be presented in both 200mm and 300mm environment. Finally, the 3D assembly will be successfully assessed through electrical and reliability tests, concretising the realism of a 3D technology for future Wide I/O products.
{"title":"Towards efficient and reliable 300mm 3D technology for wide I/O interconnects","authors":"P. Coudrain, J. Colonna, C. Aumont, G. Garnier, P. Chausse, R. Segaud, K. Vial, A. Jouve, T. Mourier, T. Magis, P. Besson, L. Gabette, C. Brunet-Manquat, N. Allouti, C. Laviron, S. Chéramy, E. Saugier, J. Pruvost, A. Farcy, N. Hotellier","doi":"10.1109/EPTC.2012.6507102","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507102","url":null,"abstract":"This paper presents the prototype of a 3D circuit with Wide I/O interconnects in a 65nm CMOS node, assembled in a face-to-back integration and reported on a BGA. The process technology carried out for the realization of the bottom die will be presented in both 200mm and 300mm environment. Finally, the 3D assembly will be successfully assessed through electrical and reliability tests, concretising the realism of a 3D technology for future Wide I/O products.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131684393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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