High performance bulk planar 20nm CMOS technology for low power mobile applications

2012 Symposium on VLSI Technology (VLSIT) Pub Date : 2012-06-12 DOI:10.1109/VLSIT.2012.6242495

H. Shang, S. Jain, E. Josse, E. Alptekin, M. Nam, S. W. Kim, K. Cho, I. Kim, Y. Liu, X. Yang, X. Wu, J. Ciavatti, N. Kim, R. Vega, L. Kang, H. Meer, S. Samavedam, M. Celik, S. Soss, H. Utomo, R. Ramachandran, W. Lai, V. Sardesai, C. Tran, J. Y. Kim, Y. H. Park, W. Tan, T. Shimizu, R. Joy, J. Strane, K. Tabakman, F. Lalanne, P. Montanini, K. Babich, J. B. Kim, L. Economikos, W. Cote, C. Reddy, M. Belyansky, R. Arndt, U. Kwon, K. Wong, D. Koli, D. Levedakis, J. Lee, J. Muncy, S. Krishnan, D. Schepis, X. Chen, B. Kim, C. Tian, B. Linder, E. Cartier, V. Narayanan, G. Northrop, O. Menut, J. Meiring, A. Thomas, M. Aminpur, S. H. Park, K. Y. Lee, B. Y. Kim, S. Rhee, B. Hamieh, R. Srivastava, R. Koshy, C. Goldberg, M. Pallachalil, M. Chae, A. Ogino, T. Watanabe, M. Oh, H. Mallela, D. Codi, P. Malinge, M. Weybright, R. Mann, A. Mittal, M. Eller, S. Lian, Y. Li, R. Divakaruni, S. Bukofsky, J. Kim, J. Sudijono, W. Neumueller, F. Matsuoka, R. Sampson

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引用次数: 22

Abstract

In this paper, we present a high performance planar 20nm CMOS bulk technology for low power mobile (LPM) computing applications featuring an advanced high-k metal gate (HKMG) process, strain engineering, 64nm metal pitch & ULK dielectrics. Compared with 28nm low power technology, it offers 0.55X density scaling and enables significant frequency improvement at lower standby power. Device drive current up to 2X 28nm at equivalent leakage is achieved through co-optimization of HKMG process and strain engineering. A fully functional, high-density (0.081um2 bit-cell) SRAM is reported with a corresponding Static Noise Margin (SNM) of 160mV at 0.9V. An advanced patterning and metallization scheme based on ULK dielectrics enables high density wiring with competitive R-C.

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用于低功耗移动应用的高性能体平面20nm CMOS技术

在本文中，我们提出了一种用于低功耗移动(LPM)计算应用的高性能平面20nm CMOS体技术，该技术具有先进的高k金属栅极(HKMG)工艺，应变工程，64nm金属间距和ULK电介质。与28nm低功耗技术相比，它提供了0.55倍的密度缩放，并在更低的待机功耗下实现了显著的频率提升。通过HKMG工艺和应变工程的共同优化，实现了等效泄漏下器件驱动电流高达2X 28nm。一种全功能、高密度(0.081um2位单元)SRAM在0.9V下具有160mV的静态噪声裕度(SNM)。基于ULK电介质的先进图像化和金属化方案使高密度布线具有竞争力的R-C。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2012 Symposium on VLSI Technology (VLSIT)

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