R. Coquand, M. Cassé, S. Barraud, P. Leroux, D. Cooper, C. Vizioz, C. Comboroure, P. Perreau, V. Maffini-Alvaro, C. Tabone, L. Tosti, F. Allain, S. Barnola, V. Delaye, F. Aussenac, Gilles Reimbold, Gérard Ghibaudo, Daniela Munteanu, S. Monfray, F. Boeuf, O. Faynot, T. Poiroux
{"title":"Strain-induced performance enhancement of tri-gate and omega-gate nanowire FETs scaled down to 10nm Width","authors":"R. Coquand, M. Cassé, S. Barraud, P. Leroux, D. Cooper, C. Vizioz, C. Comboroure, P. Perreau, V. Maffini-Alvaro, C. Tabone, L. Tosti, F. Allain, S. Barnola, V. Delaye, F. Aussenac, Gilles Reimbold, Gérard Ghibaudo, Daniela Munteanu, S. Monfray, F. Boeuf, O. Faynot, T. Poiroux","doi":"10.1109/VLSIT.2012.6242437","DOIUrl":null,"url":null,"abstract":"A detailed study of performance in uniaxially-strained Si nanowire (NW) transistors fabricated by lateral strain relaxation of biaxial SSOI substrate is presented. 2D strain imaging demonstrates the lateral strain relaxation resulting from nanoscale patterning. For the first time, an improvement of electron mobility in SSOI NW scaled down to 10nm width has been successfully demonstrated (+55% with respect to SOI NW). This improvement is maintained even by using H2 annealing used for Ω-Gate. On short gate length, a strain-induced Ion gain as high as 40% at LG=45nm is achieved for multiple-NWs active pattern.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"26","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 Symposium on VLSI Technology (VLSIT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2012.6242437","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 26
Abstract
A detailed study of performance in uniaxially-strained Si nanowire (NW) transistors fabricated by lateral strain relaxation of biaxial SSOI substrate is presented. 2D strain imaging demonstrates the lateral strain relaxation resulting from nanoscale patterning. For the first time, an improvement of electron mobility in SSOI NW scaled down to 10nm width has been successfully demonstrated (+55% with respect to SOI NW). This improvement is maintained even by using H2 annealing used for Ω-Gate. On short gate length, a strain-induced Ion gain as high as 40% at LG=45nm is achieved for multiple-NWs active pattern.
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