Gallium arsenide technology for low-power, high performance processor cores

Abstract

Recent developments in multimedia computing and communications have lead to rapid increase in performance requirements for the underlying VLSI technology which manifests itself in the development of new semiconductor materials as well as refinements in the existing ones. Not only are the circuits required to operate faster and dissipate less power, especially for portable applications, but integration of optics, i.e. image display and light detection functionality together with sophisticated signal processing in one chip becomes now a necessity and reality at the same time. The concept of personal interactive mobile multimedia communicators (M/sup 3/C) has lead to the idea of an intelligent pixel (IP) array which is effectively a video camera, a miniature display screen, and an advanced DSP processor in one device. For ultra-fast systems a considerable part of power is dissipated within a clock generation and distribution system. At the same time, at Gigahertz frequencies the clock skew becomes the factor limiting the speed of the system. This paper presents an outline of the intelligent pixel architecture and presents a detailed design methodology for highly pipelined, self-timed systems suitable for multimedia applications using Gallium Arsenide MESFET as the base technology implementation of latched logic design style (PDLL, LCFL). The use of latched logic together with the absence of the global clock provides for low power dissipation while maintaining very high speed of the system.