Y. Eom, Haksun Lee, Hyun-Cheol Bae, Kwang-Seong Choi, Jin-ho Lee
{"title":"Flip-chip bonding processes with low volume SoP technology","authors":"Y. Eom, Haksun Lee, Hyun-Cheol Bae, Kwang-Seong Choi, Jin-ho Lee","doi":"10.1109/ESTC.2014.6962857","DOIUrl":null,"url":null,"abstract":"In order to build solder bumps with a fine-pitch of 100 μm and 130 μm on PCB substrate, low volume solder on pad (LVSoP) technology using a maskless technology was developed for SAC305 solder with a high melting temperature of 220°C. For the LVSoP process, SBM (solder bump maker) material was newly developed. The solder bump maker (SBM) paste and its process were quantitatively optimized to get a uniform height of solder bumps which are almost equal to the height of solder resist. Differential scanning calorimetry (DSC), viscosity measurement and physical flowing of SBM paste were precisely investigated and analyzed during LVSoP processing for an understanding of chemo-rheological phenomena of SBM paste. The average height of solder bumps and their maximum and minimum values were 14.7, 18.3 and 12.0 μm, respectively. It is believed that maskless LVSoP technology can be effectively used for a fine-pitch interconnection of a Cu pillar in the semiconductor packaging field. Flipchip bonding process between PCB substrate with low volume solder bumps and silicon device having the cupper pillars without solder caps was performed. As one of the key solution for fine pitch interconnection with Cu pillar for Flipchip bonding process, it is expected that LVSoP technology can be effectively used in semiconductor packaging.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESTC.2014.6962857","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In order to build solder bumps with a fine-pitch of 100 μm and 130 μm on PCB substrate, low volume solder on pad (LVSoP) technology using a maskless technology was developed for SAC305 solder with a high melting temperature of 220°C. For the LVSoP process, SBM (solder bump maker) material was newly developed. The solder bump maker (SBM) paste and its process were quantitatively optimized to get a uniform height of solder bumps which are almost equal to the height of solder resist. Differential scanning calorimetry (DSC), viscosity measurement and physical flowing of SBM paste were precisely investigated and analyzed during LVSoP processing for an understanding of chemo-rheological phenomena of SBM paste. The average height of solder bumps and their maximum and minimum values were 14.7, 18.3 and 12.0 μm, respectively. It is believed that maskless LVSoP technology can be effectively used for a fine-pitch interconnection of a Cu pillar in the semiconductor packaging field. Flipchip bonding process between PCB substrate with low volume solder bumps and silicon device having the cupper pillars without solder caps was performed. As one of the key solution for fine pitch interconnection with Cu pillar for Flipchip bonding process, it is expected that LVSoP technology can be effectively used in semiconductor packaging.