Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962810
J. Krishnan, H. Sax
In semiconductor devices, the common Temperature Cyle on Board Failure (TCoB) are open contacts due solder joint cracks after 2000 to 4000 temperature cycles on board - as shown in figure 1 depending on individual ECU configuration and applied temperature swing. Recently, we also encounter TCoB reliability failure, but this solder joint cracks happen along lead rather than through the solder. For this case the failure already appeared after 850 cycles, while other components on the exactly same board do not show a sign of degradation as can be seen at figure 2 and 3. This paper objective is to describes the critical factors that impact the Temperature Cycles on Board (TCoB) performance of a solder joint. The TCoB performance of lead free solder joints does not only depend on the solder paste and package Bill Of Material (BOM) used. Quality of final Sn finish as well as lead frame pre treatment and lead frame surface properties can also impact the TCoB performance of a lead free solder joint heavily. The service life of a lead free solder joint using bare Cu lead frame together with final Sn plating can significantly be improved considering the below findings: a) Carbon in the Sn plated layer from high additive concentrations or from Carbon contaminated electrolytes have to be avoided. b) Use Plating Current density lower than 20 ASD as parasitic carbon deposition is enhanced if a too high plating current density is used (>20ASD). c) Avoid using Media Deflashing Process because the leadframe surface will be damage thus prevents good Cu diffusion from base material. Cu/Sn inter diffusion has to be promoted to form a regular low stress intermetallic where the ratio of Cu6Sn5/Cu3Sn is approximately 1. d) Removing the damage top 1-2μm Cu base material cause by Cu sheet rolling from the lead frame processing using appropriate Cu descaling process or plating an additional thick Cu flash layer (>2μm) ensures good regular low stress intermetallic.
{"title":"Impact of deflashing process and Sn plating parameters towards temperature cycle on board (TCoB) reliability","authors":"J. Krishnan, H. Sax","doi":"10.1109/ESTC.2014.6962810","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962810","url":null,"abstract":"In semiconductor devices, the common Temperature Cyle on Board Failure (TCoB) are open contacts due solder joint cracks after 2000 to 4000 temperature cycles on board - as shown in figure 1 depending on individual ECU configuration and applied temperature swing. Recently, we also encounter TCoB reliability failure, but this solder joint cracks happen along lead rather than through the solder. For this case the failure already appeared after 850 cycles, while other components on the exactly same board do not show a sign of degradation as can be seen at figure 2 and 3. This paper objective is to describes the critical factors that impact the Temperature Cycles on Board (TCoB) performance of a solder joint. The TCoB performance of lead free solder joints does not only depend on the solder paste and package Bill Of Material (BOM) used. Quality of final Sn finish as well as lead frame pre treatment and lead frame surface properties can also impact the TCoB performance of a lead free solder joint heavily. The service life of a lead free solder joint using bare Cu lead frame together with final Sn plating can significantly be improved considering the below findings: a) Carbon in the Sn plated layer from high additive concentrations or from Carbon contaminated electrolytes have to be avoided. b) Use Plating Current density lower than 20 ASD as parasitic carbon deposition is enhanced if a too high plating current density is used (>20ASD). c) Avoid using Media Deflashing Process because the leadframe surface will be damage thus prevents good Cu diffusion from base material. Cu/Sn inter diffusion has to be promoted to form a regular low stress intermetallic where the ratio of Cu6Sn5/Cu3Sn is approximately 1. d) Removing the damage top 1-2μm Cu base material cause by Cu sheet rolling from the lead frame processing using appropriate Cu descaling process or plating an additional thick Cu flash layer (>2μm) ensures good regular low stress intermetallic.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123036615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962857
Y. Eom, Haksun Lee, Hyun-Cheol Bae, Kwang-Seong Choi, Jin-ho Lee
In order to build solder bumps with a fine-pitch of 100 μm and 130 μm on PCB substrate, low volume solder on pad (LVSoP) technology using a maskless technology was developed for SAC305 solder with a high melting temperature of 220°C. For the LVSoP process, SBM (solder bump maker) material was newly developed. The solder bump maker (SBM) paste and its process were quantitatively optimized to get a uniform height of solder bumps which are almost equal to the height of solder resist. Differential scanning calorimetry (DSC), viscosity measurement and physical flowing of SBM paste were precisely investigated and analyzed during LVSoP processing for an understanding of chemo-rheological phenomena of SBM paste. The average height of solder bumps and their maximum and minimum values were 14.7, 18.3 and 12.0 μm, respectively. It is believed that maskless LVSoP technology can be effectively used for a fine-pitch interconnection of a Cu pillar in the semiconductor packaging field. Flipchip bonding process between PCB substrate with low volume solder bumps and silicon device having the cupper pillars without solder caps was performed. As one of the key solution for fine pitch interconnection with Cu pillar for Flipchip bonding process, it is expected that LVSoP technology can be effectively used in semiconductor packaging.
{"title":"Flip-chip bonding processes with low volume SoP technology","authors":"Y. Eom, Haksun Lee, Hyun-Cheol Bae, Kwang-Seong Choi, Jin-ho Lee","doi":"10.1109/ESTC.2014.6962857","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962857","url":null,"abstract":"In order to build solder bumps with a fine-pitch of 100 μm and 130 μm on PCB substrate, low volume solder on pad (LVSoP) technology using a maskless technology was developed for SAC305 solder with a high melting temperature of 220°C. For the LVSoP process, SBM (solder bump maker) material was newly developed. The solder bump maker (SBM) paste and its process were quantitatively optimized to get a uniform height of solder bumps which are almost equal to the height of solder resist. Differential scanning calorimetry (DSC), viscosity measurement and physical flowing of SBM paste were precisely investigated and analyzed during LVSoP processing for an understanding of chemo-rheological phenomena of SBM paste. The average height of solder bumps and their maximum and minimum values were 14.7, 18.3 and 12.0 μm, respectively. It is believed that maskless LVSoP technology can be effectively used for a fine-pitch interconnection of a Cu pillar in the semiconductor packaging field. Flipchip bonding process between PCB substrate with low volume solder bumps and silicon device having the cupper pillars without solder caps was performed. As one of the key solution for fine pitch interconnection with Cu pillar for Flipchip bonding process, it is expected that LVSoP technology can be effectively used in semiconductor packaging.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114301039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962800
Vinh Cao Duy, Hoang-Vu Nguyen, H. Kristiansen, M. Taklo, K. Aasmundtveit, N. Hoivik
This paper investigates an approach for creating a metallurgic bond between Ø5 μm metal (Au)-coated polymer spheres (MPS) and Indium (In) pads. MPS were positioned onto In pads where the metal coating reacted with the In. The MPS were deposited by dry dispensing. The adhesion force between the MPS and the In pads was measured by acceleration/centrifugal testing. Under a centrifugal force of 34 nN, the percentage of remaining MPS increased from 10 % for samples without heat treatment to more than 90 % for samples exposed to 200 °C annealing. This is a strong indication that a metallurgic bond had formed between the metal coating on the MPS and the In on the pads.
{"title":"Immobilization of metal coated polymer spheres on Indium pads","authors":"Vinh Cao Duy, Hoang-Vu Nguyen, H. Kristiansen, M. Taklo, K. Aasmundtveit, N. Hoivik","doi":"10.1109/ESTC.2014.6962800","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962800","url":null,"abstract":"This paper investigates an approach for creating a metallurgic bond between Ø5 μm metal (Au)-coated polymer spheres (MPS) and Indium (In) pads. MPS were positioned onto In pads where the metal coating reacted with the In. The MPS were deposited by dry dispensing. The adhesion force between the MPS and the In pads was measured by acceleration/centrifugal testing. Under a centrifugal force of 34 nN, the percentage of remaining MPS increased from 10 % for samples without heat treatment to more than 90 % for samples exposed to 200 °C annealing. This is a strong indication that a metallurgic bond had formed between the metal coating on the MPS and the In on the pads.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124612720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962842
M. Wiesenfarth, Sebastian Gamisch, Tobias Dorsam, A. Bett
In concentrating photovoltaics (CPV) solar radiation is concentrated up to 1000 times using inexpensive optics. This leads to high heat flux in the system of up to 100 W/cm2 and requires an efficient thermal design. There are actively and passively cooled systems. The thermal design of those systems is investigated with theoretical simulations. In this paper we present how to validate the simulations using indoor experiments. To manufacture CPV modules industrially, standard processes from the electronic industry like wire bonding or pick-and-place are used and adapted wherever possible. In this paper a process to mount solar cells with areas >1 cm2 using vacuum soldering is presented. For the integration of bypass diodes, the assembly adjacent or the use of special solar cell architectures like the MIMs are proposed.
{"title":"Challenges for thermal management and production technologies in concentrating photovoltaic (CPV) modules","authors":"M. Wiesenfarth, Sebastian Gamisch, Tobias Dorsam, A. Bett","doi":"10.1109/ESTC.2014.6962842","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962842","url":null,"abstract":"In concentrating photovoltaics (CPV) solar radiation is concentrated up to 1000 times using inexpensive optics. This leads to high heat flux in the system of up to 100 W/cm2 and requires an efficient thermal design. There are actively and passively cooled systems. The thermal design of those systems is investigated with theoretical simulations. In this paper we present how to validate the simulations using indoor experiments. To manufacture CPV modules industrially, standard processes from the electronic industry like wire bonding or pick-and-place are used and adapted wherever possible. In this paper a process to mount solar cells with areas >1 cm2 using vacuum soldering is presented. For the integration of bypass diodes, the assembly adjacent or the use of special solar cell architectures like the MIMs are proposed.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129476829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962727
T. Brunschwiler, R. Heller, G. Schlottig, T. Tick, H. Harrer, H. Barowski, Tim Niggemeier, J. Supper, S. Oggioni
In this paper, a novel concept of dual-side electrical interconnects (EIC) to a chip stack is discussed. In this concept, a second laminate, called Thermal Power Plane (TPP), is attached through solder rails to the top chip of the stack. The TPP provides efficient heat removal and current feed in the out-of-plane and the in-plane direction, respectively. Accordingly, the number of electrical interconnects to the chip stack can be doubled, enabling higher off-stack communication. An interconnect count analysis was performed for a two-die stack with cores in the top and cache in the bottom chip. The power to the top and the bottom chip is provided from the TPP and the bottom laminate, respectively. In this case, all power through-silicon vias (TSVs) can be eliminated, which would otherwise cover 3.3% of the bottom chip area. In addition, the design of the TSVs can be optimized for signaling only. The use of two laminates also enables individual test & burn-in of the dies prior to stack formation, potentially improving the yield by joining only known good dies. The feasibility of the concept is supported by thermal and electrical finite-element analysis. An 8-layer coreless laminate with stacked build-up vias, extending between both sides of the substrate, was considered as implementation of the TPP. The thermal performance of the dual-side EIC topology outperforms that of the classical single-side EIC approach by 5 Kmm2/W, when considering bar-shaped copper planes in the TPP and elongated top interconnects, called rails. A voltage uniformity to the top chip of better than 2% of the supply voltage can be provided for all TPP designs.
{"title":"Thermal power plane enabling dual-side electrical interconnects for high-performance chip stacks: Concept","authors":"T. Brunschwiler, R. Heller, G. Schlottig, T. Tick, H. Harrer, H. Barowski, Tim Niggemeier, J. Supper, S. Oggioni","doi":"10.1109/ESTC.2014.6962727","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962727","url":null,"abstract":"In this paper, a novel concept of dual-side electrical interconnects (EIC) to a chip stack is discussed. In this concept, a second laminate, called Thermal Power Plane (TPP), is attached through solder rails to the top chip of the stack. The TPP provides efficient heat removal and current feed in the out-of-plane and the in-plane direction, respectively. Accordingly, the number of electrical interconnects to the chip stack can be doubled, enabling higher off-stack communication. An interconnect count analysis was performed for a two-die stack with cores in the top and cache in the bottom chip. The power to the top and the bottom chip is provided from the TPP and the bottom laminate, respectively. In this case, all power through-silicon vias (TSVs) can be eliminated, which would otherwise cover 3.3% of the bottom chip area. In addition, the design of the TSVs can be optimized for signaling only. The use of two laminates also enables individual test & burn-in of the dies prior to stack formation, potentially improving the yield by joining only known good dies. The feasibility of the concept is supported by thermal and electrical finite-element analysis. An 8-layer coreless laminate with stacked build-up vias, extending between both sides of the substrate, was considered as implementation of the TPP. The thermal performance of the dual-side EIC topology outperforms that of the classical single-side EIC approach by 5 Kmm2/W, when considering bar-shaped copper planes in the TPP and elongated top interconnects, called rails. A voltage uniformity to the top chip of better than 2% of the supply voltage can be provided for all TPP designs.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124005080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962821
R. Soukup, T. Blecha, A. Hamácek, J. Řeboun
This paper presents a research focused on a smart textile-based protective system which is intended to bring more safety to firefighters facing hazardous conditions. The system is fully integrated into a firefighter protective suit and it is able to monitor heart rate (HR), to detect movements of a firefighter, to detect toxic and combustible gases in the environment and to measure temperature (T) and relative humidity (RH) inside and outside of the suit. The protective system consists of developed integrated sensor modules, e-textile wiring harnesses, body control unit (BCU), central processing unit (CPU), body area network (BAN) and wide area network (WAN). The measured data are wirelessly transmitted over a wide area network with automatic routing algorithm to the central processing unit, which is checked by a firefighter operation chief, who is kept informed about an actual state of individual fire fighters. In case that some monitored parameter oversteps pre-set threshold values the BCU will automatically inform a fire fighter by means of acoustic alarm about oncoming risk.
{"title":"Smart textile-based protective system for firefighters","authors":"R. Soukup, T. Blecha, A. Hamácek, J. Řeboun","doi":"10.1109/ESTC.2014.6962821","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962821","url":null,"abstract":"This paper presents a research focused on a smart textile-based protective system which is intended to bring more safety to firefighters facing hazardous conditions. The system is fully integrated into a firefighter protective suit and it is able to monitor heart rate (HR), to detect movements of a firefighter, to detect toxic and combustible gases in the environment and to measure temperature (T) and relative humidity (RH) inside and outside of the suit. The protective system consists of developed integrated sensor modules, e-textile wiring harnesses, body control unit (BCU), central processing unit (CPU), body area network (BAN) and wide area network (WAN). The measured data are wirelessly transmitted over a wide area network with automatic routing algorithm to the central processing unit, which is checked by a firefighter operation chief, who is kept informed about an actual state of individual fire fighters. In case that some monitored parameter oversteps pre-set threshold values the BCU will automatically inform a fire fighter by means of acoustic alarm about oncoming risk.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116305900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962846
Aurelien Lecavelier des Etangs-Levallois, A. Grivon, D. Baudet, W. Maia, M. Brizoux
An alternative to lead-free soldering may be Electrically Conductive Adhesives (ECA) that feature lower soldering temperature. However, long-term electrical properties stability and reliability in harsh environment shall be studied. The work presented here is a comprehensive study of ECA second level interconnects characterization under thermal and thermo-mechanical stress for different PCB and component finishing.
{"title":"Reliability analysis of electronic assemblies using electrically conductive adhesive for high-reliability and Harsh environment applications","authors":"Aurelien Lecavelier des Etangs-Levallois, A. Grivon, D. Baudet, W. Maia, M. Brizoux","doi":"10.1109/ESTC.2014.6962846","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962846","url":null,"abstract":"An alternative to lead-free soldering may be Electrically Conductive Adhesives (ECA) that feature lower soldering temperature. However, long-term electrical properties stability and reliability in harsh environment shall be studied. The work presented here is a comprehensive study of ECA second level interconnects characterization under thermal and thermo-mechanical stress for different PCB and component finishing.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126343292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962741
B. Khorramdel, M. Mantysalo
Through silicon vias (TSVs) have been used in 3D packaging of microelectronic devices and MEMS devices, where they provide electrical interconnections through the stacked wafers and devices. Currently, chemical vapor deposition (CVD) or electroless deposition are used to partially or fulfill the vias. However, these methods are time consuming. Thus, the potential of inkjet printing to linearly fill the TSVs with silver nanoparticle ink, as an additive digital fabrication technique, will be reviewed. This technique could make the via metallization process much faster, agile, and cost-efficient. In this study, vias with the outer diameter of 80μm and depth of around 115μm fabricated with dry-reactive ion etching (DRIE) are filled with a silver nano-particle ink NPS-J from Harima Chemicals using Dimatix inkjet printer (DMP-2800) with 10pl cartridge. Substrate temperature was found to be potentially more affective to print more droplets rather than increasing waiting time. Moreover, printing on the 60 °C substrate with no delay was optimum considering the uniformity, thickness and quality of the coverage.
通过硅通孔(tsv)已用于微电子器件和MEMS器件的3D封装，其中它们通过堆叠的晶圆和器件提供电气互连。目前，化学气相沉积(CVD)或化学沉积(CVD)被用于部分或完成过孔。然而，这些方法都很耗时。因此，作为一种增材数字制造技术，喷墨印刷将银纳米颗粒油墨线性填充tsv的潜力将被回顾。这种技术可以使金属化过程更快、更灵活、更经济。在本研究中，使用Dimatix喷墨打印机(DMP-2800)和10pl墨盒，采用干反应离子蚀刻(dry reactive ion etching, DRIE)技术制备了外径80μm、深度约115μm的Harima Chemicals纳米银粒子油墨NPS-J。发现衬底温度可能对打印更多液滴更有影响，而不是增加等待时间。此外，考虑到覆盖的均匀性、厚度和质量，在60°C的基材上无延迟印刷是最佳的。
{"title":"Inkjet filling of TSVs with silver nanoparticle ink","authors":"B. Khorramdel, M. Mantysalo","doi":"10.1109/ESTC.2014.6962741","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962741","url":null,"abstract":"Through silicon vias (TSVs) have been used in 3D packaging of microelectronic devices and MEMS devices, where they provide electrical interconnections through the stacked wafers and devices. Currently, chemical vapor deposition (CVD) or electroless deposition are used to partially or fulfill the vias. However, these methods are time consuming. Thus, the potential of inkjet printing to linearly fill the TSVs with silver nanoparticle ink, as an additive digital fabrication technique, will be reviewed. This technique could make the via metallization process much faster, agile, and cost-efficient. In this study, vias with the outer diameter of 80μm and depth of around 115μm fabricated with dry-reactive ion etching (DRIE) are filled with a silver nano-particle ink NPS-J from Harima Chemicals using Dimatix inkjet printer (DMP-2800) with 10pl cartridge. Substrate temperature was found to be potentially more affective to print more droplets rather than increasing waiting time. Moreover, printing on the 60 °C substrate with no delay was optimum considering the uniformity, thickness and quality of the coverage.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"3 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130286849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962860
T. Blank, B. Leyrer, T. Maurer, M. Meisser, M. Bruns, M. Weber
Substrates for high power electronic systems are dominated by DCB-technology. Recently, new copper thick-film pastes have been proposed for use as high power substrates. They are compatible with Al2O3- and pre-oxised AlN-substrates. This paper investigates production processes to build up highly reliable power modules and explores basis electrical and thermal properties of thick-film copper substrates. Fired copper film thicknesses of 300 μm have been produced by subsequent print-dry-fire cycles. Smooth surfaces and copper films with a density of about 70 % of bulk copper have been produced. A power module comprising of 650 V IGBTs, diodes and an intelligent hall sensor with copper traces and spaces of 200 μm is presented. Wire bonding processes on copper thick-films with 500 μm aluminium wire and 400 μm copper wire are discussed. Test units with a 1200 V IGBT were built up. The IGBT was attached at 250 °C and a pressure of 15 MPa using a novel silver sinter paste. This paste can be directly used on copper. The current-carrying capacity of the thick-film test samples was found to be reduced by 10% in comparison to the DCB test device. No significant difference was found in the performance of both technologies in active power pulse tests lasting a few seconds. The number of cycles for test devices with sintered chips, bonded with 400 μm copper wire bonds exceeded 450,000 cycles in a cycles from 25 °C up to 150 °C.
{"title":"Copper thick-film substrates for power electronic applications","authors":"T. Blank, B. Leyrer, T. Maurer, M. Meisser, M. Bruns, M. Weber","doi":"10.1109/ESTC.2014.6962860","DOIUrl":"https://doi.org/10.1109/ESTC.2014.6962860","url":null,"abstract":"Substrates for high power electronic systems are dominated by DCB-technology. Recently, new copper thick-film pastes have been proposed for use as high power substrates. They are compatible with Al2O3- and pre-oxised AlN-substrates. This paper investigates production processes to build up highly reliable power modules and explores basis electrical and thermal properties of thick-film copper substrates. Fired copper film thicknesses of 300 μm have been produced by subsequent print-dry-fire cycles. Smooth surfaces and copper films with a density of about 70 % of bulk copper have been produced. A power module comprising of 650 V IGBTs, diodes and an intelligent hall sensor with copper traces and spaces of 200 μm is presented. Wire bonding processes on copper thick-films with 500 μm aluminium wire and 400 μm copper wire are discussed. Test units with a 1200 V IGBT were built up. The IGBT was attached at 250 °C and a pressure of 15 MPa using a novel silver sinter paste. This paste can be directly used on copper. The current-carrying capacity of the thick-film test samples was found to be reduced by 10% in comparison to the DCB test device. No significant difference was found in the performance of both technologies in active power pulse tests lasting a few seconds. The number of cycles for test devices with sintered chips, bonded with 400 μm copper wire bonds exceeded 450,000 cycles in a cycles from 25 °C up to 150 °C.","PeriodicalId":299981,"journal":{"name":"Proceedings of the 5th Electronics System-integration Technology Conference (ESTC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115708749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/ESTC.2014.6962790
R. Pufall, M. Goroll, G. M. Reuther
Thermo-mechanical stress caused by the mismatch of coefficients of thermal expansion (CTE) and temperature variations remain a major concern for the reliability of semiconductor components. This issue is usually addressed by exposing the component to temperature cycling stress tests for a certain number of cycles, followed by e.g. scanning acoustic microscopy (SAM) to investigate delamination. Discussions about specific cycling conditions, e.g. using -65 °C/+175 °C instead of -55 °C/+150 °C for the minimum and maximum temperatures of the cycles or even using liquid-liquid instead of air to air cycling to speed up investigations [1], are often moot, because no real understanding of the effect of the cycling conditions on the component is available. Furthermore, it is almost a truism that testing alone does not suffice to ensure the reliability of a component. Reliability has to be built into the components from the beginning. As a consequence, the question should be turned around: it is not enough to look at delamination after a certain number of cycles in a stress test. The question is rather how the component should be designed and how the materials should be chosen to prevent delamination. Thus, the focus is changed from measuring delamination to measuring adhesion. In the previous paper [6] an approach for a better understanding of adhesion in terms of possible material combinations, temperature influence (ageing, delamination due to critical induced stress) and topology of interfaces was presented. This paper focuses on methods to reduce interfacial stresses in order to reduce the risk of delamination.
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