On the Static CMOS Implementation of Magnitude Comparators

2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2019-07-01 DOI:10.1109/PATMOS.2019.8862135

C. Efstathiou, Y. Tsiatouhas

引用次数: 5

Abstract

Digital magnitude comparators are used in computer systems to compare two binary numbers and determine if these are equal, or if one number is greater or less than the other. In this work, a new magnitude comparator’s architecture is presented. The proposed comparator architecture is designed in static CMOS logic and compared against the state of the art magnitude comparators in the literature, shows less area overhead, and for small input operands (which are commonly used in practice) presents lower delay and power-delay product.

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幅度比较器的静态CMOS实现

数字幅度比较器在计算机系统中用于比较两个二进制数并确定它们是否相等，或者一个数是否大于或小于另一个数。在这项工作中，提出了一种新的幅度比较器结构。所提出的比较器架构采用静态CMOS逻辑设计，并与文献中最先进的幅度比较器进行比较，显示出更少的面积开销，并且对于小输入操作数(在实践中常用)具有更低的延迟和功率延迟积。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)

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