Pub Date : 2019-07-01DOI: 10.1109/patmos.2019.8862035
{"title":"[PATMOS 2019 Title Page]","authors":"","doi":"10.1109/patmos.2019.8862035","DOIUrl":"https://doi.org/10.1109/patmos.2019.8862035","url":null,"abstract":"","PeriodicalId":430458,"journal":{"name":"2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114991355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/patmos.2019.8862003
{"title":"PATMOS 2019 Committees","authors":"","doi":"10.1109/patmos.2019.8862003","DOIUrl":"https://doi.org/10.1109/patmos.2019.8862003","url":null,"abstract":"","PeriodicalId":430458,"journal":{"name":"2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123823557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/PATMOS.2019.8862056
A. Stefanidis, Dimitrios Mangiras, C. Nicopoulos, G. Dimitrakopoulos
Timing closure is a complex process that involves many iterative optimization steps applied in various phases of the physical design flow. Cell sizing and transistor threshold selection, as well as datapath and clock buffering, are some of the tools available for design optimization. At the moment, design optimization methods are integrated into EDA tools and applied incrementally in various parts of the flow, while the optimal order of their application is yet to be determined. In this work, we rely on reinforcement learning – through the use of the Multi-Armed Bandit model for decision making under uncertainty – to automatically suggest online which optimization heuristic should be applied to the design. The goal is to improve the performance metrics based on the rewards learned from the previous applications of each heuristic. Experimental results show that automating the process of design optimization with machine learning not only results in designs that are close to the best-published results derived from deterministic approaches, but it also allows for the execution of the optimization flow without any human in the loop, and without any need for offline training of the heuristic-orchestration algorithm.
{"title":"Multi-Armed Bandits for Autonomous Timing-driven Design Optimization","authors":"A. Stefanidis, Dimitrios Mangiras, C. Nicopoulos, G. Dimitrakopoulos","doi":"10.1109/PATMOS.2019.8862056","DOIUrl":"https://doi.org/10.1109/PATMOS.2019.8862056","url":null,"abstract":"Timing closure is a complex process that involves many iterative optimization steps applied in various phases of the physical design flow. Cell sizing and transistor threshold selection, as well as datapath and clock buffering, are some of the tools available for design optimization. At the moment, design optimization methods are integrated into EDA tools and applied incrementally in various parts of the flow, while the optimal order of their application is yet to be determined. In this work, we rely on reinforcement learning – through the use of the Multi-Armed Bandit model for decision making under uncertainty – to automatically suggest online which optimization heuristic should be applied to the design. The goal is to improve the performance metrics based on the rewards learned from the previous applications of each heuristic. Experimental results show that automating the process of design optimization with machine learning not only results in designs that are close to the best-published results derived from deterministic approaches, but it also allows for the execution of the optimization flow without any human in the loop, and without any need for offline training of the heuristic-orchestration algorithm.","PeriodicalId":430458,"journal":{"name":"2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123831829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/PATMOS.2019.8862170
Bastian Koppelmann, Peer Adelt, W. Mueller, C. Scheytt
Embedded systems require a high energy efficiency in combination with an optimized performance. As such, Bit Manipulation Instructions (BMIs) were introduced for x86 and ARMv8 to improve the runtime efficiency and power dissipation of the compiled software for various applications. Though the RISC-V platform is meanwhile widely accepted for embedded systems application, its instruction set architecture (ISA) currently still supports only two basic BMIs.We introduce ten advanced BMIs for the RISC-V ISA and implemented them on Berkeley’s Rocket CPU [1], which we synthesized for the Artix-7 FPGA and the TSMC 65nm cell library. Our RISC-V BMI definitions are based on an analysis and combination of existing x86 and ARMv8 BMIs. Our Rocket CPU hardware extensions show that RISC-V BMI extensions have no negative impact on the critical path of the execution pipeline. Our software evaluations show that we can, for example, expect a significant impact for time and power consuming cryptographic applications.
{"title":"RISC-V Extensions for Bit Manipulation Instructions","authors":"Bastian Koppelmann, Peer Adelt, W. Mueller, C. Scheytt","doi":"10.1109/PATMOS.2019.8862170","DOIUrl":"https://doi.org/10.1109/PATMOS.2019.8862170","url":null,"abstract":"Embedded systems require a high energy efficiency in combination with an optimized performance. As such, Bit Manipulation Instructions (BMIs) were introduced for x86 and ARMv8 to improve the runtime efficiency and power dissipation of the compiled software for various applications. Though the RISC-V platform is meanwhile widely accepted for embedded systems application, its instruction set architecture (ISA) currently still supports only two basic BMIs.We introduce ten advanced BMIs for the RISC-V ISA and implemented them on Berkeley’s Rocket CPU [1], which we synthesized for the Artix-7 FPGA and the TSMC 65nm cell library. Our RISC-V BMI definitions are based on an analysis and combination of existing x86 and ARMv8 BMIs. Our Rocket CPU hardware extensions show that RISC-V BMI extensions have no negative impact on the critical path of the execution pipeline. Our software evaluations show that we can, for example, expect a significant impact for time and power consuming cryptographic applications.","PeriodicalId":430458,"journal":{"name":"2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132384572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/PATMOS.2019.8862063
C. Rheinländer, N. Wehn
Energy harvesting has emerged as a promising technology for small electronic devices to extend the battery run time and thereby enabling an increased autonomous operation. However, frequent charge and discharge cycles cause aging effects in the battery, which results in a loss of capacity and life time.Power-neutral transient computing systems avoid energy buffers by powering the load by the harvester directly. Usually, the power outputs of energy harvesters rely on arbitrary and transient environmental excitations. The resulting power losses are handled by checkpointing, where the volatile system state is backed up using non-volatile memories. The timely detection of upcoming power losses is essential for a reliable checkpointing process. Early detections allow a proactive power loss handling, which is important to ensure the finalization of atomic operations. However, common voltage threshold-based methods only allow short-term power loss detections since they do not adapt to the dynamics of the harvester.In this paper we propose a new methodology that allows an early power loss detection by exploiting physical characteristics of the harvester. The proposed approach points out new opportunities for transiently-powered devices, as it allows an adaptive and harvester-aware computing. We show how it facilitates a proactive scheduling that is used to ensure a successful finalization of atomic operations.
{"title":"Adaptive Transient Computing for Power-Neutral Embedded Devices","authors":"C. Rheinländer, N. Wehn","doi":"10.1109/PATMOS.2019.8862063","DOIUrl":"https://doi.org/10.1109/PATMOS.2019.8862063","url":null,"abstract":"Energy harvesting has emerged as a promising technology for small electronic devices to extend the battery run time and thereby enabling an increased autonomous operation. However, frequent charge and discharge cycles cause aging effects in the battery, which results in a loss of capacity and life time.Power-neutral transient computing systems avoid energy buffers by powering the load by the harvester directly. Usually, the power outputs of energy harvesters rely on arbitrary and transient environmental excitations. The resulting power losses are handled by checkpointing, where the volatile system state is backed up using non-volatile memories. The timely detection of upcoming power losses is essential for a reliable checkpointing process. Early detections allow a proactive power loss handling, which is important to ensure the finalization of atomic operations. However, common voltage threshold-based methods only allow short-term power loss detections since they do not adapt to the dynamics of the harvester.In this paper we propose a new methodology that allows an early power loss detection by exploiting physical characteristics of the harvester. The proposed approach points out new opportunities for transiently-powered devices, as it allows an adaptive and harvester-aware computing. We show how it facilitates a proactive scheduling that is used to ensure a successful finalization of atomic operations.","PeriodicalId":430458,"journal":{"name":"2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131259705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/PATMOS.2019.8862036
I. Kouretas, Vassilis Paliouras
This paper introduces a family of radix-3 modulo-M multipliers. Following the description of a high-radix modulo multiplication algorithm, a set of low-complexity digit adders are introduced and subsequently used to compose the proposed modulo multipliers. Complexity reduction of the particular digit adders is achieved by exploiting the limited set of the possible values assumed by the inputs. The proposed modulo-M multipliers are derived by means of a graph-based optimization algorithm which selects the appropriate digit adders from a set of possible choices to produce minimal complexity solutions. The proposed multipliers are synthesized using a 0.18μm 1.8V CMOS standard-cell library. Comparisons to previously reported radix-2 and radix-3 modulo multipliers reveal that the proposed multipliers achieve complexity savings in terms of area, delay and area × delay complexities for certain moduli.
{"title":"Radix-3 low-complexity modulo-M multipliers","authors":"I. Kouretas, Vassilis Paliouras","doi":"10.1109/PATMOS.2019.8862036","DOIUrl":"https://doi.org/10.1109/PATMOS.2019.8862036","url":null,"abstract":"This paper introduces a family of radix-3 modulo-M multipliers. Following the description of a high-radix modulo multiplication algorithm, a set of low-complexity digit adders are introduced and subsequently used to compose the proposed modulo multipliers. Complexity reduction of the particular digit adders is achieved by exploiting the limited set of the possible values assumed by the inputs. The proposed modulo-M multipliers are derived by means of a graph-based optimization algorithm which selects the appropriate digit adders from a set of possible choices to produce minimal complexity solutions. The proposed multipliers are synthesized using a 0.18μm 1.8V CMOS standard-cell library. Comparisons to previously reported radix-2 and radix-3 modulo multipliers reveal that the proposed multipliers achieve complexity savings in terms of area, delay and area × delay complexities for certain moduli.","PeriodicalId":430458,"journal":{"name":"2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116268360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/patmos.2019.8862077
{"title":"PATMOS 2019 Welcome Message","authors":"","doi":"10.1109/patmos.2019.8862077","DOIUrl":"https://doi.org/10.1109/patmos.2019.8862077","url":null,"abstract":"","PeriodicalId":430458,"journal":{"name":"2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127047060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/PATMOS.2019.8862146
A. Boursianis, Maria S. Papadopoulou, P. Damantoulakis, Apostolia Karampatea, P. Doanis, D. Geourgoulas, A. Skoufa, D. Valavanis, C. Apostolidis, D. Babas, K. Baltzis, T. Kaifas, K. Siozios, S. Siskos, T. Samaras, K. Siakavara, S. Nikolaidis, S. Goudos, A. Liopa-Tsakalidi, P. Barouchas, I. Kasimis, G. Kalamaras, D. Merkouris, G. Perrakis, C. Tsirogiannis, A. Gotsis, K. Maliatsos
Water scarcity and desertification are considered to be among the greatest challenges of humanity over the coming decades. Worldwide, agriculture accounts to 69% of total water usage, while industry accounts for 23%, and urban use to 8%. In Greece, a rural development model and poor farming practices have resulted in an overwhelming 83% of total water consumption to be directed to farming uses. Furthermore, excessive use of water in agriculture combined with existing pesticides and fertilizers usage levels creates exponential problems in the water cycle in Greece. Taking into account the above challenges, the AREThOU5A Project aims to exploit the state-of-the-art technologies and, in particular, the emerging developments in the field of Internet of Things (IoT) as a means to promote rational use of water resources in agriculture. In particular, AREThOU5A Project aims at accelerating penetration of low-power wide-access (LPWA) technologies through a series of research and innovation actions focusing on the design, development, operation and commercial exploitation of relevant hardware/software & IoT applications. Preliminary results of the AREThOU5A Project are depicted and future remarks are outlined.
{"title":"Advancing Rational Exploitation of Water Irrigation Using 5G-IoT Capabilities: The AREThOU5A Project","authors":"A. Boursianis, Maria S. Papadopoulou, P. Damantoulakis, Apostolia Karampatea, P. Doanis, D. Geourgoulas, A. Skoufa, D. Valavanis, C. Apostolidis, D. Babas, K. Baltzis, T. Kaifas, K. Siozios, S. Siskos, T. Samaras, K. Siakavara, S. Nikolaidis, S. Goudos, A. Liopa-Tsakalidi, P. Barouchas, I. Kasimis, G. Kalamaras, D. Merkouris, G. Perrakis, C. Tsirogiannis, A. Gotsis, K. Maliatsos","doi":"10.1109/PATMOS.2019.8862146","DOIUrl":"https://doi.org/10.1109/PATMOS.2019.8862146","url":null,"abstract":"Water scarcity and desertification are considered to be among the greatest challenges of humanity over the coming decades. Worldwide, agriculture accounts to 69% of total water usage, while industry accounts for 23%, and urban use to 8%. In Greece, a rural development model and poor farming practices have resulted in an overwhelming 83% of total water consumption to be directed to farming uses. Furthermore, excessive use of water in agriculture combined with existing pesticides and fertilizers usage levels creates exponential problems in the water cycle in Greece. Taking into account the above challenges, the AREThOU5A Project aims to exploit the state-of-the-art technologies and, in particular, the emerging developments in the field of Internet of Things (IoT) as a means to promote rational use of water resources in agriculture. In particular, AREThOU5A Project aims at accelerating penetration of low-power wide-access (LPWA) technologies through a series of research and innovation actions focusing on the design, development, operation and commercial exploitation of relevant hardware/software & IoT applications. Preliminary results of the AREThOU5A Project are depicted and future remarks are outlined.","PeriodicalId":430458,"journal":{"name":"2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127876512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/PATMOS.2019.8862135
C. Efstathiou, Y. Tsiatouhas
Digital magnitude comparators are used in computer systems to compare two binary numbers and determine if these are equal, or if one number is greater or less than the other. In this work, a new magnitude comparator’s architecture is presented. The proposed comparator architecture is designed in static CMOS logic and compared against the state of the art magnitude comparators in the literature, shows less area overhead, and for small input operands (which are commonly used in practice) presents lower delay and power-delay product.
{"title":"On the Static CMOS Implementation of Magnitude Comparators","authors":"C. Efstathiou, Y. Tsiatouhas","doi":"10.1109/PATMOS.2019.8862135","DOIUrl":"https://doi.org/10.1109/PATMOS.2019.8862135","url":null,"abstract":"Digital magnitude comparators are used in computer systems to compare two binary numbers and determine if these are equal, or if one number is greater or less than the other. In this work, a new magnitude comparator’s architecture is presented. The proposed comparator architecture is designed in static CMOS logic and compared against the state of the art magnitude comparators in the literature, shows less area overhead, and for small input operands (which are commonly used in practice) presents lower delay and power-delay product.","PeriodicalId":430458,"journal":{"name":"2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114340533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/PATMOS.2019.8862161
Mingjie Hao, Ardalan Najafi, A. Ortiz, Ludwig Karsthof, S. Paul, Jochen Rust
In the last decade, approximate computing has gained a lot of research attention as one of the most promising energy-efficient computing paradigms. In the meantime, the wireless communication development driven by the ongoing paradigm shift of Industry 4.0 (I40) and Industrial Internet of Things (IIoT) has been growing enormously. This paper presents a use case study of the impact of approximate adders in industrial wireless communication. The results show the uncorrelation between the traditional metrics used to optimize approximate units and the actual impact at the system level.
{"title":"Reliability of an Industrial Wireless Communication System using Approximate Units","authors":"Mingjie Hao, Ardalan Najafi, A. Ortiz, Ludwig Karsthof, S. Paul, Jochen Rust","doi":"10.1109/PATMOS.2019.8862161","DOIUrl":"https://doi.org/10.1109/PATMOS.2019.8862161","url":null,"abstract":"In the last decade, approximate computing has gained a lot of research attention as one of the most promising energy-efficient computing paradigms. In the meantime, the wireless communication development driven by the ongoing paradigm shift of Industry 4.0 (I40) and Industrial Internet of Things (IIoT) has been growing enormously. This paper presents a use case study of the impact of approximate adders in industrial wireless communication. The results show the uncorrelation between the traditional metrics used to optimize approximate units and the actual impact at the system level.","PeriodicalId":430458,"journal":{"name":"2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116692810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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