A comparative study up to 1024 bit Euclid's GCD algorithm FPGA implementation and synthesizing

Abstract

In this paper, we are targeting Altera Cyclone IV FPGA family to design an efficient GCD (Greatest Common Divisor) coprocessor based on Euclid's method with variable datapath sizes. The design was synthesized using seven chip technologies in terms of maximum frequency and critical path delay of the coprocessor. As a result, the comparison between different FPGA devices shows that Xilinx devices XC7VH290T-2-HCG1155 as well as XC7K70T-2-FBG676 recorded the best values of maximum frequencies of243.934 MHz down to 39.94 MHz for 32 bit and 1024 bit datapaths, respectively. Finally, the comparison with previous designs illustrates that the proposed coprocessor design has a throughput efficiency of even two times faster than other designs. Hence, the proposed work will help the FPGA system designers to better utilize the hardware performance for many applications such as cryptosystems design.