ESD effects on power supply clamps [CMOS ICs]

Abstract

Electrostatic discharge (ESD) damage is a common failure mechanism that is seen on CMOS integrated circuit devices. Due to the ever increasing shrinkage in transistor geometries, prevention of ESD damage will become increasingly important. This paper discusses the various device level ESD in the form of power supply clamps. There are numerous power supply clamps that are currently available such as the grounded gate, thick field oxide (TFO), diode string and cantilever diode structures. Selection of the right ESD power supply clamp is essential from the aspects of their limitations, weaknesses, silicon space and effectiveness to ensure robustness during to ESD stresses on devices.