Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638194
C. Maneux, N. Labat, N. Saysset, A. Touboul, Y. Danto, J. Dumas, P. Launay, J. Dangla
A field-induced degradation mechanism responsible for the surface current drift in GaAs HBT is identified on the basis of accelerated ageing tests under bias. Degradations of ohmic contact and metallisation are highlighted under high temperature storage. These results bring further evidence of both bias and temperature-induced degradation mechanisms in GaAs HBTs. As a consequence, a specific life test strategy similar to that implemented for FETs has been derived.
{"title":"Analysis of GaAs HBT failure mechanisms: impact on life test strategy","authors":"C. Maneux, N. Labat, N. Saysset, A. Touboul, Y. Danto, J. Dumas, P. Launay, J. Dangla","doi":"10.1109/IPFA.1997.638194","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638194","url":null,"abstract":"A field-induced degradation mechanism responsible for the surface current drift in GaAs HBT is identified on the basis of accelerated ageing tests under bias. Degradations of ohmic contact and metallisation are highlighted under high temperature storage. These results bring further evidence of both bias and temperature-induced degradation mechanisms in GaAs HBTs. As a consequence, a specific life test strategy similar to that implemented for FETs has been derived.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"299 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123043394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638069
J. Tao, W. Chim, D.S.H. Chan, J. Phang, Y.Y. Liu
Two normalisation methods have been introduced for the analysis and quantification of device spectral signatures obtained from the spectroscopic photon emission microscope (SPEMS). The parameter: /spl lambda//sub 1.0/ and /spl lambda//sub 50%/, having clear spectral distribution for different devices or mechanisms involved, were found to be useful in device failure analysis. It is also found that these wavelength parameters are dependent on the internal electric fields of the device. Hence, these can be used as an alternative method of monitoring electric fields in devices.
{"title":"Analysis and quantification of device spectral signatures observed using a spectroscopic photon emission microscope","authors":"J. Tao, W. Chim, D.S.H. Chan, J. Phang, Y.Y. Liu","doi":"10.1109/IPFA.1997.638069","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638069","url":null,"abstract":"Two normalisation methods have been introduced for the analysis and quantification of device spectral signatures obtained from the spectroscopic photon emission microscope (SPEMS). The parameter: /spl lambda//sub 1.0/ and /spl lambda//sub 50%/, having clear spectral distribution for different devices or mechanisms involved, were found to be useful in device failure analysis. It is also found that these wavelength parameters are dependent on the internal electric fields of the device. Hence, these can be used as an alternative method of monitoring electric fields in devices.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116385199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638068
T. Ishii, M. Inoue, N. Asatani, K. Naitoh, J. Mitsuhashi
A novel technique has been developed for fault isolation in logic LSIs. The technique is constructed using backside infra-red light detection through the silicon chip by an emission microscope, which is connected to an automated test equipment (ATE), and linked to a CAD layout pattern view system which assists the chip backside image and logic simulation for fault verification. This technique can perform an exact functional failure analysis from the backside of the chip.
{"title":"Functional failure analysis of logic LSIs from backside of the chip and its verification by logic simulation","authors":"T. Ishii, M. Inoue, N. Asatani, K. Naitoh, J. Mitsuhashi","doi":"10.1109/IPFA.1997.638068","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638068","url":null,"abstract":"A novel technique has been developed for fault isolation in logic LSIs. The technique is constructed using backside infra-red light detection through the silicon chip by an emission microscope, which is connected to an automated test equipment (ATE), and linked to a CAD layout pattern view system which assists the chip backside image and logic simulation for fault verification. This technique can perform an exact functional failure analysis from the backside of the chip.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126887130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638174
C. Lou, W. Qin, W. Chim, D. Chan
Hot-carrier injection is observed to increasingly degrade the subthreshold characteristics with the scaling of LDD PMOSFETs. A physical subthreshold current model is applied to the fresh and hot-carrier stressed submicrometer channel length devices. The generated interface traps and channel length reduction are subsequently extracted. An empirical model is developed to characterize the degradation parameters as a function of stress time and channel length. With the use of this model, we can determine the degradation parameters and hence predict the minimum allowable channel length (for a certain percentage of degradation and lifetime) that is applicable for a specific technology.
{"title":"Modelling the hot-carrier induced degradation in the subthreshold characteristics of submicrometer LDD PMOSFETs","authors":"C. Lou, W. Qin, W. Chim, D. Chan","doi":"10.1109/IPFA.1997.638174","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638174","url":null,"abstract":"Hot-carrier injection is observed to increasingly degrade the subthreshold characteristics with the scaling of LDD PMOSFETs. A physical subthreshold current model is applied to the fresh and hot-carrier stressed submicrometer channel length devices. The generated interface traps and channel length reduction are subsequently extracted. An empirical model is developed to characterize the degradation parameters as a function of stress time and channel length. With the use of this model, we can determine the degradation parameters and hence predict the minimum allowable channel length (for a certain percentage of degradation and lifetime) that is applicable for a specific technology.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127772766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638124
Y. Ousten, S. Mejdi, A. Fenech, J. Delétage, L. Béchou, M. Perichaud, Y. Danto
We propose complementary solutions to improve the evaluation of PCB under specific stresses using electrical and physical indicators adapted to a given part of the board. For ceramic capacitors, the residual piezoelectricity provides an impedance signature at resonance allowing detection of local physical defects. Solder joint fatigue criticity under thermal cycle can be predicted using combined analytical and FEM simulations, while the lead phases coarsening provides a good early degradation indicator. At last, ball inspection of BGA packages using shear waves in scanning acoustic microscope lead to an interesting improvement of resolution.
{"title":"The use of impedance spectroscopy, SEM and SAM imaging for early detection of failure in SMT assemblies","authors":"Y. Ousten, S. Mejdi, A. Fenech, J. Delétage, L. Béchou, M. Perichaud, Y. Danto","doi":"10.1109/IPFA.1997.638124","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638124","url":null,"abstract":"We propose complementary solutions to improve the evaluation of PCB under specific stresses using electrical and physical indicators adapted to a given part of the board. For ceramic capacitors, the residual piezoelectricity provides an impedance signature at resonance allowing detection of local physical defects. Solder joint fatigue criticity under thermal cycle can be predicted using combined analytical and FEM simulations, while the lead phases coarsening provides a good early degradation indicator. At last, ball inspection of BGA packages using shear waves in scanning acoustic microscope lead to an interesting improvement of resolution.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125657757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638353
J. Remes, H. Moilanen, S. Leppavuori
The fast-turnaround ASIC prototype series must be brought into market quickly. Unfortunately, it is often noticed that, despite through simulations, design flaws are introduced into these circuits. The reason for the failure is either in the design or in some processing error. These flaws may usually be corrected by redesigning the layout and putting the IC through a semiconductor fabrication process again which is costly and time consuming. In this work LCVD of copper from Cu(hfac)tmvs has been utilised for the restructuring of IC interconnections. Copper lines were deposited onto passivated ICs in order to achieve new local interconnections between IC structures. The resistivities of the deposited lines were found to be close to copper bulk resistivity. The utilisation of Nd:YAG and XeCl excimer lasers in the cutting of conductor lines is also described. Special practical IC repair case problems and solutions carried out by LCVD system are presented.
{"title":"Fast first-run silicon repair cases by laser chemical vapor deposition of copper from Cu(hfac)tmvs","authors":"J. Remes, H. Moilanen, S. Leppavuori","doi":"10.1109/IPFA.1997.638353","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638353","url":null,"abstract":"The fast-turnaround ASIC prototype series must be brought into market quickly. Unfortunately, it is often noticed that, despite through simulations, design flaws are introduced into these circuits. The reason for the failure is either in the design or in some processing error. These flaws may usually be corrected by redesigning the layout and putting the IC through a semiconductor fabrication process again which is costly and time consuming. In this work LCVD of copper from Cu(hfac)tmvs has been utilised for the restructuring of IC interconnections. Copper lines were deposited onto passivated ICs in order to achieve new local interconnections between IC structures. The resistivities of the deposited lines were found to be close to copper bulk resistivity. The utilisation of Nd:YAG and XeCl excimer lasers in the cutting of conductor lines is also described. Special practical IC repair case problems and solutions carried out by LCVD system are presented.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130445449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638345
X. Liu, D. Chan, J. Phang, W. Chim
In this paper, we describe the observation of a new phenomenon which may be extended to provide a non electrical and physical evaluation of the electrical stress degradation of Si-SiO/sub 2/ structures. Two novel observations, the hot-electron-injection-induced 2.7 eV luminescence centers and the interfacial stress dependence of the 2.7 eV CL peak build-up, are described.
在本文中，我们描述了一种新现象的观察结果，该现象可以扩展到对Si-SiO/sub - 2/结构的电应力退化提供非电学和物理评价。本文描述了两个新的观察结果，即热电子注入诱导的2.7 eV发光中心和2.7 eV CL峰积累对界面应力的依赖。
{"title":"Cathodoluminescence evaluation of electrical stress condition of Si-SiO/sub 2/ structures","authors":"X. Liu, D. Chan, J. Phang, W. Chim","doi":"10.1109/IPFA.1997.638345","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638345","url":null,"abstract":"In this paper, we describe the observation of a new phenomenon which may be extended to provide a non electrical and physical evaluation of the electrical stress degradation of Si-SiO/sub 2/ structures. Two novel observations, the hot-electron-injection-induced 2.7 eV luminescence centers and the interfacial stress dependence of the 2.7 eV CL peak build-up, are described.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132286647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638193
B. Jie, M. Li, C. Lou, K. Lo, W. Chim, D. Chan
A direct-current current-voltage (DCIV) technique for the measurement of interface traps and oxide charges in LDD pMOSFETs with n-well in p-substrate is demonstrated. The interface trap densities are monitored using the bulk current of the MOS transistor. The DCIV results for pMOSFETs after substrate hot carrier injection and channel hot carrier injection are presented and analyzed. There are two peaks in the DCIV spectrum after channel hot carrier injection, corresponding to hot-carrier-generated interface traps located in the channel region and the lightly-doped drain (LDD) region respectively. The stress-induced oxide charge results in the shifts of two peaks.
{"title":"Direct-current measurements of interface traps and oxide charges in LDD pMOSFETs with an n-well structure","authors":"B. Jie, M. Li, C. Lou, K. Lo, W. Chim, D. Chan","doi":"10.1109/IPFA.1997.638193","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638193","url":null,"abstract":"A direct-current current-voltage (DCIV) technique for the measurement of interface traps and oxide charges in LDD pMOSFETs with n-well in p-substrate is demonstrated. The interface trap densities are monitored using the bulk current of the MOS transistor. The DCIV results for pMOSFETs after substrate hot carrier injection and channel hot carrier injection are presented and analyzed. There are two peaks in the DCIV spectrum after channel hot carrier injection, corresponding to hot-carrier-generated interface traps located in the channel region and the lightly-doped drain (LDD) region respectively. The stress-induced oxide charge results in the shifts of two peaks.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116464045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638349
M. Natarajan, C. Q. Cui, D.P. Poener, M. Radhakrishnan
This paper presents the results of a few case studies carried out on semiconductor devices and packaging related materials. The emphasis is on the novel application of Scanning Probe Microscopy (SPM) techniques as compared to the traditional analysis. Also, application of two surface topography parameters of SPM, power spectral density and total surface area are briefly discussed.
{"title":"Applications of atomic force microscopy for semiconductor device and package characterization","authors":"M. Natarajan, C. Q. Cui, D.P. Poener, M. Radhakrishnan","doi":"10.1109/IPFA.1997.638349","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638349","url":null,"abstract":"This paper presents the results of a few case studies carried out on semiconductor devices and packaging related materials. The emphasis is on the novel application of Scanning Probe Microscopy (SPM) techniques as compared to the traditional analysis. Also, application of two surface topography parameters of SPM, power spectral density and total surface area are briefly discussed.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124806302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638196
K. Aw
Inconsistency in power down current (IPD) measurement was experienced on the device, with Word Line Charge Pump, when it is operating at Vcc higher than 3 V. When the device enters power down, the current was measured in a very random manner, sometimes down to sub-micro-ampere or a few ten micro-ampere range. This problem totally goes away when the device is operating at 3 V. The root cause of this problem is due to the VCO (Voltage Control Oscillator) of the Word Line Charge Pump.
在使用Word Line Charge Pump的设备上，当其工作在高于3v的Vcc时，出现了断电电流(IPD)测量不一致的情况。当器件进入断电状态时，电流以一种非常随机的方式测量，有时下降到亚微安或几十微安的范围。当设备在3v电压下工作时，这个问题就完全消失了。这个问题的根本原因是由于VCO(电压控制振荡器)的字线电荷泵。
{"title":"Inconsistency in power down current caused by voltage control oscillator (VCO) of EPROM wordline charge pump","authors":"K. Aw","doi":"10.1109/IPFA.1997.638196","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638196","url":null,"abstract":"Inconsistency in power down current (IPD) measurement was experienced on the device, with Word Line Charge Pump, when it is operating at Vcc higher than 3 V. When the device enters power down, the current was measured in a very random manner, sometimes down to sub-micro-ampere or a few ten micro-ampere range. This problem totally goes away when the device is operating at 3 V. The root cause of this problem is due to the VCO (Voltage Control Oscillator) of the Word Line Charge Pump.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129958162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：