Automated BIST-based diagnostic solution for SOPC

Abstract

This paper presents a diagnostic methodology to detect and locate faulty embedded cores IP cores in modern FPGAs. Parameterized Verilog models have been developed to apply the algorithm. Built-in sell-test (BIST) generation and synthesis performed in an automated flow for any given device. The approach is applicable to different cores including, block RAM, multiplier, DSP, etc. and is it scalable to different devices. The technique utilizes existing hardware redundancy and reconfigurability of an FPGA to achieve testability and diagnosis resolution without imposing any cost, area overhead or performance degradation. Experimental results show its efficiency in facilitating failure analysis process and expediting debugging procedure. It can also be applied to offline system testing and diagnosis for fault-tolerant applications