Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708730
C. P. Moreira, E. Kerhervé, P. Jarry, D. Belor
The authors present in this article a dual-standard dual-mode low-noise amplifier (LNA) for DCS1800/W-CDMA-FDD applications. In order to save die area compared to conventional parallel LNAs, an alternative circuit configuration have been used. It consists of sharing the most die consuming elements (inductances) in both operation standards, enabling a more compact solution. The mode and standard selection is performed through a bias scheme (MOS switches) that allows alternating between the two involved standards. The LNA die area is 1.0 times 1.2 mm2 and it consumes 6.8mW (3.8mA under 1.8V), including bias circuitry
{"title":"A dual-mode dual-standard LNA for DCS1800/W-CDMA applications","authors":"C. P. Moreira, E. Kerhervé, P. Jarry, D. Belor","doi":"10.1109/DTIS.2006.1708730","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708730","url":null,"abstract":"The authors present in this article a dual-standard dual-mode low-noise amplifier (LNA) for DCS1800/W-CDMA-FDD applications. In order to save die area compared to conventional parallel LNAs, an alternative circuit configuration have been used. It consists of sharing the most die consuming elements (inductances) in both operation standards, enabling a more compact solution. The mode and standard selection is performed through a bias scheme (MOS switches) that allows alternating between the two involved standards. The LNA die area is 1.0 times 1.2 mm2 and it consumes 6.8mW (3.8mA under 1.8V), including bias circuitry","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126829762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708666
Hedi Abdelkrim, S. Ben Saoud
Since some years, most of the architectures of autonomous robots integrate the planning activity, which provides goals for the robot, with behavior-based reactivity, implemented by simple and fast control modules. The purpose of this article is the implementation of a tracking path algorithm based fuzzy logic on a field programmable gate array
{"title":"Implementation of a fuzzy logic tracking path algorithm on a field programmable gate array","authors":"Hedi Abdelkrim, S. Ben Saoud","doi":"10.1109/DTIS.2006.1708666","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708666","url":null,"abstract":"Since some years, most of the architectures of autonomous robots integrate the planning activity, which provides goals for the robot, with behavior-based reactivity, implemented by simple and fast control modules. The purpose of this article is the implementation of a tracking path algorithm based fuzzy logic on a field programmable gate array","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116564155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708664
M. A. Sacristán, Victoria Rodellar, Antonio Díaz
This paper describes the behavior of the synthesis of several adders with different structures: lineal, like ripple carry adder, tree, like carry look ahead; array, like prefix adders; and optimized low level logic over FPGAs. The results of used resources and total delay of the resulting circuit are compared over the commercial families VIRTEX4 and STRATIX2 from Xilinx and Altera manufacturers, respectively
{"title":"Comparison of addition structures synthesis over commercial FPGAs","authors":"M. A. Sacristán, Victoria Rodellar, Antonio Díaz","doi":"10.1109/DTIS.2006.1708664","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708664","url":null,"abstract":"This paper describes the behavior of the synthesis of several adders with different structures: lineal, like ripple carry adder, tree, like carry look ahead; array, like prefix adders; and optimized low level logic over FPGAs. The results of used resources and total delay of the resulting circuit are compared over the commercial families VIRTEX4 and STRATIX2 from Xilinx and Altera manufacturers, respectively","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117266332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708654
A. Benso, A. Bosio, P. Prinetto, A. Savino
Software-based self-test (SBST) in embedded microprocessor cores testing allows lowering test costs without loosing fault detection capabilities. Particularly in critical environments, SBST is executed during the system operating life in order to guarantee its availability and quality of service. If the test routines can be executed online but not-concurrently, then both the hardware and software overheads are negligible. This paper presents results and issues faced during the development of SBST approach targeting a Motorola PowerPC 603 core. The test, constrained by tight timing and coverage requirements, required the development of a general framework, easily reusable on other microprocessor cores
{"title":"An on-line software-based self-test framework for microprocessor cores","authors":"A. Benso, A. Bosio, P. Prinetto, A. Savino","doi":"10.1109/DTIS.2006.1708654","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708654","url":null,"abstract":"Software-based self-test (SBST) in embedded microprocessor cores testing allows lowering test costs without loosing fault detection capabilities. Particularly in critical environments, SBST is executed during the system operating life in order to guarantee its availability and quality of service. If the test routines can be executed online but not-concurrently, then both the hardware and software overheads are negligible. This paper presents results and issues faced during the development of SBST approach targeting a Motorola PowerPC 603 core. The test, constrained by tight timing and coverage requirements, required the development of a general framework, easily reusable on other microprocessor cores","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128650574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708674
H. Daoud, S. B. Salem, S. Zouari, M. Loulou
This paper deals with design and optimization of a folded cascode operational transconductance amplifier. First, a detailed description of an optimum OTA topology is done in order to optimize MOS transistor sizing. Second, the design of folded cascode OTA, which works for frequencies that lead to a base band circuit design for RF application, is based on transistor sizing methodology. Third, folded cascode OTAs generally find several applications that are well developed. Simulation results are performed using SPICE software and BSIM3V3 model for CMOS 0.35mum process, show that the designed folded cascode OTA has a 85dB DC gain and provides a gain bandwidth product of around 332MHz
{"title":"Folded cascode OTA design for wide band applications","authors":"H. Daoud, S. B. Salem, S. Zouari, M. Loulou","doi":"10.1109/DTIS.2006.1708674","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708674","url":null,"abstract":"This paper deals with design and optimization of a folded cascode operational transconductance amplifier. First, a detailed description of an optimum OTA topology is done in order to optimize MOS transistor sizing. Second, the design of folded cascode OTA, which works for frequencies that lead to a base band circuit design for RF application, is based on transistor sizing methodology. Third, folded cascode OTAs generally find several applications that are well developed. Simulation results are performed using SPICE software and BSIM3V3 model for CMOS 0.35mum process, show that the designed folded cascode OTA has a 85dB DC gain and provides a gain bandwidth product of around 332MHz","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129171840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708669
S. Hamza Sfar, I. Bennour, R. Tourki
The increasing of SoC complexity and the need of performance, encourage designers to implement network on chip rather than point to point connection or shared bus. NoC borrows many concepts to computer network and includes enough complexity to be transaction level modeled. But first, we must precise both system design flow and NoC characteristics to be modeled
{"title":"Transaction level modeling of an OSI-like layered NoC","authors":"S. Hamza Sfar, I. Bennour, R. Tourki","doi":"10.1109/DTIS.2006.1708669","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708669","url":null,"abstract":"The increasing of SoC complexity and the need of performance, encourage designers to implement network on chip rather than point to point connection or shared bus. NoC borrows many concepts to computer network and includes enough complexity to be transaction level modeled. But first, we must precise both system design flow and NoC characteristics to be modeled","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121107924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708703
R. Iraji, S. Hessabi, E.K. Moghadam
The ODYSSEY design methodology is an object-oriented design methodology which models a system in terms of its constituting objects and their corresponding method calls. Some of these method calls are implemented in hardware functional units, while others are simply executed by a general-purpose processor. There is a communication overhead because functional units must communicate with each other and with the processor core. In this paper the authors utilize the custom instructions capability of Nios II processor to enhance the performance of the ASIP. Since these instructions are in the processor itself, there is no communication overhead for using them. The authors analyze the performance of the proposed method by implementing the Rijndael algorithm with and without this capability, and show the achieved speedup
{"title":"Accelerating the Rijndael algorithm using custom instructions capability of Nios II in ODYSSEY","authors":"R. Iraji, S. Hessabi, E.K. Moghadam","doi":"10.1109/DTIS.2006.1708703","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708703","url":null,"abstract":"The ODYSSEY design methodology is an object-oriented design methodology which models a system in terms of its constituting objects and their corresponding method calls. Some of these method calls are implemented in hardware functional units, while others are simply executed by a general-purpose processor. There is a communication overhead because functional units must communicate with each other and with the processor core. In this paper the authors utilize the custom instructions capability of Nios II processor to enhance the performance of the ASIP. Since these instructions are in the processor itself, there is no communication overhead for using them. The authors analyze the performance of the proposed method by implementing the Rijndael algorithm with and without this capability, and show the achieved speedup","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125656776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708701
J. Lorival, D. Deschacht, Y. Quéré, T. Gouguec, F. Huret
Constant evolution in integrated circuit technology has led to an increase in the switching speed of the digital chip. As a result, there is a growing interest in the inductance associated with signal lines. Inductive coupling effects on interconnects is an emerging concern in high performance digital integrated circuits. Based on an RLC transmission line model, associated to each propagation mode, a new crosstalk noise model is proposed to evaluate both the capacitive and the inductive coupling. The additivity of the coupling is shown and validated with several simulations
{"title":"Additivity of capacitive and inductive coupling in submicronic interconnects","authors":"J. Lorival, D. Deschacht, Y. Quéré, T. Gouguec, F. Huret","doi":"10.1109/DTIS.2006.1708701","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708701","url":null,"abstract":"Constant evolution in integrated circuit technology has led to an increase in the switching speed of the digital chip. As a result, there is a growing interest in the inductance associated with signal lines. Inductive coupling effects on interconnects is an emerging concern in high performance digital integrated circuits. Based on an RLC transmission line model, associated to each propagation mode, a new crosstalk noise model is proposed to evaluate both the capacitive and the inductive coupling. The additivity of the coupling is shown and validated with several simulations","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133200343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708690
M. Masmoudi, I. Song, F. Karray, M. Masmoudi, N. Derbel
This paper presents different approaches to design and implement a fuzzy logic controller (FLC) for an intelligent parking system (IPS). In recent years fuzzy logic has been adopted for scientific and engineering applications. FLC is particularly successful in the area of system control when human expert knowledge is available. It provides an alternative much simpler than the use of an analytical model. FLC can be implemented on an FPGA (field-programmable gate array) using software or hardware approach. With the software approach, FLC is performed on a flexible FPGA soft core processor. The FLC is developed and tested on a reconfigurable FPGA board
{"title":"Hardware/software approache for the FPGA implementation of a fuzzy logic controller","authors":"M. Masmoudi, I. Song, F. Karray, M. Masmoudi, N. Derbel","doi":"10.1109/DTIS.2006.1708690","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708690","url":null,"abstract":"This paper presents different approaches to design and implement a fuzzy logic controller (FLC) for an intelligent parking system (IPS). In recent years fuzzy logic has been adopted for scientific and engineering applications. FLC is particularly successful in the area of system control when human expert knowledge is available. It provides an alternative much simpler than the use of an analytical model. FLC can be implemented on an FPGA (field-programmable gate array) using software or hardware approach. With the software approach, FLC is performed on a flexible FPGA soft core processor. The FLC is developed and tested on a reconfigurable FPGA board","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124439460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-10-16DOI: 10.1109/DTIS.2006.1708649
G. B. Hmida, M. Dhieb, H. Ghariani, M. Samet
The electronic implants were introduced in the human body further to a surgical operation for the neurological dysfunctions treatment as well as the help or the replacement of the organs which have difficulties. For practical and medical reasons, implants have to communicate without wire with the external world. Most of them use an inductive link to supply in power and data. In this paper, we propose a communication system for the medical implants which uses inductive link. This system is consisted of a class E power amplifier, an ASK modulator, an inductive link and an ASK demodulator
{"title":"Transcutaneous power and high data rate transmission for biomedical implants","authors":"G. B. Hmida, M. Dhieb, H. Ghariani, M. Samet","doi":"10.1109/DTIS.2006.1708649","DOIUrl":"https://doi.org/10.1109/DTIS.2006.1708649","url":null,"abstract":"The electronic implants were introduced in the human body further to a surgical operation for the neurological dysfunctions treatment as well as the help or the replacement of the organs which have difficulties. For practical and medical reasons, implants have to communicate without wire with the external world. Most of them use an inductive link to supply in power and data. In this paper, we propose a communication system for the medical implants which uses inductive link. This system is consisted of a class E power amplifier, an ASK modulator, an inductive link and an ASK demodulator","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125875715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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