{"title":"Test structures for debugging variation of critical devices caused by layout-dependent effects in FinFETs","authors":"Qi Lin, Hans Pan, Jonathan Chang","doi":"10.1109/ICMTS.2018.8383751","DOIUrl":null,"url":null,"abstract":"The increasing stress engineering in FinFETs raises concerns about performance variation caused by the strong layout-dependent effect (LDE). The challenge is that it is difficult to decouple the combination of LDEs in a layout. As a result, it is challenging for Fab to reduce the variation induced by LDE. In this paper, we present a set of test structures for monitoring and debugging the variation of critical devices caused by LDEs. These test structures were verified in 16nm FinFET technology. We also present two case studies of debugging FinFET device variation by using these test structures.","PeriodicalId":271839,"journal":{"name":"2018 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Conference on Microelectronic Test Structures (ICMTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMTS.2018.8383751","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
The increasing stress engineering in FinFETs raises concerns about performance variation caused by the strong layout-dependent effect (LDE). The challenge is that it is difficult to decouple the combination of LDEs in a layout. As a result, it is challenging for Fab to reduce the variation induced by LDE. In this paper, we present a set of test structures for monitoring and debugging the variation of critical devices caused by LDEs. These test structures were verified in 16nm FinFET technology. We also present two case studies of debugging FinFET device variation by using these test structures.
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