Pub Date : 2018-06-12DOI: 10.1109/ICMTS.2018.8383799
Yukiko Ishijima, S. Nakagawa, H. Ishikuro
Time reduction technique for the measurement of input referred noise of dynamic comparator is presented. By using binary search technique, the proposed method can reduce the measurement time of comparator input referred noise to (log2n)/n, where n is a required resolution. Experimental results obtained by the developed measurement system shows good correspondence with the simulated input referred noise.
{"title":"Measurement time reduction technique for input referred noise of dynamic comparator","authors":"Yukiko Ishijima, S. Nakagawa, H. Ishikuro","doi":"10.1109/ICMTS.2018.8383799","DOIUrl":"https://doi.org/10.1109/ICMTS.2018.8383799","url":null,"abstract":"Time reduction technique for the measurement of input referred noise of dynamic comparator is presented. By using binary search technique, the proposed method can reduce the measurement time of comparator input referred noise to (log2n)/n, where n is a required resolution. Experimental results obtained by the developed measurement system shows good correspondence with the simulated input referred noise.","PeriodicalId":271839,"journal":{"name":"2018 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115513404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-19DOI: 10.1109/ICMTS.2018.8383753
Hyeong-Sub Song, Dong-Jun Oh, So-Yeong Kim, Sungkyu Kwon, Sung-Jin Choi, D. Kim, D. Lim, Changhwan Choi, D. M. Kim, H. Lee
In this paper, we proposed novel test structures to evaluate the distribution of interface state density of MOSFETs by using optical charge pumping method. Unlike other measurement methods to extract interface state density (Dit), which have a limited range of measurable energy states and influenced by gate area and gate leakage, Dit can be extracted without these problems by using the proposed test structures. Test structures were fabricated using a 0.18μ CMOS process or FD-SOI technology with high-k dielectric, respectively. Optical charge pumping was performed in proposed test structures and Dit is extracted from 109 cm−2· eV−1 to 1013 cm−2· eV−1.
{"title":"Novel test structures for extracting interface state density of advanced CMOSFETs using optical charge pumping","authors":"Hyeong-Sub Song, Dong-Jun Oh, So-Yeong Kim, Sungkyu Kwon, Sung-Jin Choi, D. Kim, D. Lim, Changhwan Choi, D. M. Kim, H. Lee","doi":"10.1109/ICMTS.2018.8383753","DOIUrl":"https://doi.org/10.1109/ICMTS.2018.8383753","url":null,"abstract":"In this paper, we proposed novel test structures to evaluate the distribution of interface state density of MOSFETs by using optical charge pumping method. Unlike other measurement methods to extract interface state density (Dit), which have a limited range of measurable energy states and influenced by gate area and gate leakage, Dit can be extracted without these problems by using the proposed test structures. Test structures were fabricated using a 0.18μ CMOS process or FD-SOI technology with high-k dielectric, respectively. Optical charge pumping was performed in proposed test structures and Dit is extracted from 10<sup>9</sup> cm<sup>−2</sup>· eV<sup>−1</sup> to 10<sup>13</sup> cm<sup>−2</sup>· eV<sup>−1</sup>.","PeriodicalId":271839,"journal":{"name":"2018 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127417677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-19DOI: 10.1109/ICMTS.2018.8383787
S. Mun, J. Cho, B. Zhu, P. Agnihotri, C. Y. Wong, T. Lee, V. Mahajan, B. Liu, Y. Shi, W. Hong, J. Ciavatti, J. G. Lee, S. Samavedam, D. K. Sohn
The quantitative model of effective total capacitance, Ceff, of a CMOS ring oscillator (R/O) inverter chain in a 14nm node FinFET 3D structure using advanced Replacement Metal Gate (RMG) is successfully extracted using all the unit capacitance components comprising the R/O, such as inverter, fan-out (F/O) MOSCAP, and metal routing. The extracted Ceff model is well validated by perfect matching to the measured Si Ceff in the R/O. This paper provides a concise and clear Ceff quantitative model of inverter R/O chain using individual transistor capacitance components such as channel capacitance (Cgc), overlap capacitance (Cov), junction capacitance (Cj) and metal wire capacitance (Cwire) considering the R/O layout and its operation mechanism, which has never been reported before. Furthermore, Cov is decomposed with the gate to contact capacitance (Cmol), EPI source-drain (S/D) to gate on Fin top (Cft), EPI S/D to gate on Fin sidewall (Cfb) and intrinsic gate to S/D overlap capacitance (Cdo) with Si data and simulation. Contribution to Ceff by all the capacitor components from Cgc, Cmol, Cj, Cwire, Cft, Cfb and Cdo is extracted with Si validation. Cov reduction without DC performance degradation is also provided in this paper.
{"title":"Quantitative model of CMOS inverter chain ring oscillator's effective capacitance and its improvements in 14nm FinFET technology","authors":"S. Mun, J. Cho, B. Zhu, P. Agnihotri, C. Y. Wong, T. Lee, V. Mahajan, B. Liu, Y. Shi, W. Hong, J. Ciavatti, J. G. Lee, S. Samavedam, D. K. Sohn","doi":"10.1109/ICMTS.2018.8383787","DOIUrl":"https://doi.org/10.1109/ICMTS.2018.8383787","url":null,"abstract":"The quantitative model of effective total capacitance, Ceff, of a CMOS ring oscillator (R/O) inverter chain in a 14nm node FinFET 3D structure using advanced Replacement Metal Gate (RMG) is successfully extracted using all the unit capacitance components comprising the R/O, such as inverter, fan-out (F/O) MOSCAP, and metal routing. The extracted Ceff model is well validated by perfect matching to the measured Si Ceff in the R/O. This paper provides a concise and clear Ceff quantitative model of inverter R/O chain using individual transistor capacitance components such as channel capacitance (Cgc), overlap capacitance (Cov), junction capacitance (Cj) and metal wire capacitance (Cwire) considering the R/O layout and its operation mechanism, which has never been reported before. Furthermore, Cov is decomposed with the gate to contact capacitance (Cmol), EPI source-drain (S/D) to gate on Fin top (Cft), EPI S/D to gate on Fin sidewall (Cfb) and intrinsic gate to S/D overlap capacitance (Cdo) with Si data and simulation. Contribution to Ceff by all the capacitor components from Cgc, Cmol, Cj, Cwire, Cft, Cfb and Cdo is extracted with Si validation. Cov reduction without DC performance degradation is also provided in this paper.","PeriodicalId":271839,"journal":{"name":"2018 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117099540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-19DOI: 10.1109/ICMTS.2018.8383761
E. Demircan, M. Shroff, Hsun-Cheng Lee
As VLSI technology features are pushed to the limit with every generation and with the introduction of new materials and increased current densities to satisfy performance demands, failure risk due to Electromigraton (EM) is ever-increasing. In this paper, we present experimental results using a novel set of test structures to validate a new model-based EM risk assessment approach. In this method, EM risk can be assessed for any interconnect geometry through an exact solution of the fundamental stress equations. This approach eliminates the need for complex look-up tables for different geometries and can be implemented in CAD tools very easily as we demonstrate on real design examples.
{"title":"Test structure design for model-based electromigration","authors":"E. Demircan, M. Shroff, Hsun-Cheng Lee","doi":"10.1109/ICMTS.2018.8383761","DOIUrl":"https://doi.org/10.1109/ICMTS.2018.8383761","url":null,"abstract":"As VLSI technology features are pushed to the limit with every generation and with the introduction of new materials and increased current densities to satisfy performance demands, failure risk due to Electromigraton (EM) is ever-increasing. In this paper, we present experimental results using a novel set of test structures to validate a new model-based EM risk assessment approach. In this method, EM risk can be assessed for any interconnect geometry through an exact solution of the fundamental stress equations. This approach eliminates the need for complex look-up tables for different geometries and can be implemented in CAD tools very easily as we demonstrate on real design examples.","PeriodicalId":271839,"journal":{"name":"2018 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115216994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-19DOI: 10.1109/ICMTS.2018.8383766
C. Dover, A. Ross, S. Smith, J. Terry, A. Mount, A. Walton
This paper presents a full wafer test structure, designed to quantify the effect of seed layer thickness and conductivity on the plating uniformity of patterned electroplated structures. The test structure enables the effect of IR drop on the electroplated film to be evaluated and provides information to help facilitate the optimisation of seed layer thickness.
{"title":"Test structures for seed layer optimisation of electroplated ferromagnetic films","authors":"C. Dover, A. Ross, S. Smith, J. Terry, A. Mount, A. Walton","doi":"10.1109/ICMTS.2018.8383766","DOIUrl":"https://doi.org/10.1109/ICMTS.2018.8383766","url":null,"abstract":"This paper presents a full wafer test structure, designed to quantify the effect of seed layer thickness and conductivity on the plating uniformity of patterned electroplated structures. The test structure enables the effect of IR drop on the electroplated film to be evaluated and provides information to help facilitate the optimisation of seed layer thickness.","PeriodicalId":271839,"journal":{"name":"2018 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129915103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-19DOI: 10.1109/ICMTS.2018.8383765
S. Venica, F. Driussi, A. Gahoi, S. Kataria, P. Palestri, Max C. Lenirne, Luca Scimi
The transfer Length Method is a well-estab experimental technique to characterize the contact resista semiconductor devices. However, its dependability is ques for metal-graphene contacts. We investigate in-depth the si cal error of the extracted contact resistance values and we strategies to limit such error and to obtain reliable result method has been successfully applied to samples with dil contact metals.
{"title":"Reliability analysis of the metal-graphene contact resistance extracted by the transfer length method","authors":"S. Venica, F. Driussi, A. Gahoi, S. Kataria, P. Palestri, Max C. Lenirne, Luca Scimi","doi":"10.1109/ICMTS.2018.8383765","DOIUrl":"https://doi.org/10.1109/ICMTS.2018.8383765","url":null,"abstract":"The transfer Length Method is a well-estab experimental technique to characterize the contact resista semiconductor devices. However, its dependability is ques for metal-graphene contacts. We investigate in-depth the si cal error of the extracted contact resistance values and we strategies to limit such error and to obtain reliable result method has been successfully applied to samples with dil contact metals.","PeriodicalId":271839,"journal":{"name":"2018 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124002357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-19DOI: 10.1109/ICMTS.2018.8383759
Michihiro Shintani, Masayuki Hiromoto, Takashi Sato
A novel parameter extraction method for compact MOSFET models is proposed. The proposed method exploits automatic differentiation (AD) technique that is widely used in the training of artificial neural networks. In the AD technique, gradient of all the parameters of the MOSFET model is analytically calculated as a graph to reduce computational cost. On the basis of the calculated gradient, the model parameters are efficiently optimized. Through experiments using SPICE models, the parameter extraction using the proposed method achieved 7.01x speedup compared to that using the numerical-differentiation method.
{"title":"Efficient parameter-extraction of SPICE compact model through automatic differentiation","authors":"Michihiro Shintani, Masayuki Hiromoto, Takashi Sato","doi":"10.1109/ICMTS.2018.8383759","DOIUrl":"https://doi.org/10.1109/ICMTS.2018.8383759","url":null,"abstract":"A novel parameter extraction method for compact MOSFET models is proposed. The proposed method exploits automatic differentiation (AD) technique that is widely used in the training of artificial neural networks. In the AD technique, gradient of all the parameters of the MOSFET model is analytically calculated as a graph to reduce computational cost. On the basis of the calculated gradient, the model parameters are efficiently optimized. Through experiments using SPICE models, the parameter extraction using the proposed method achieved 7.01x speedup compared to that using the numerical-differentiation method.","PeriodicalId":271839,"journal":{"name":"2018 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"22 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133387953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-19DOI: 10.1109/ICMTS.2018.8383798
C. Yadav, M. Deng, M. De matos, S. Frégonèse, T. Zimmer
In this paper, we present the effect of different sub-mm and mm-wave probe geometry and topology on the measurement results of dedicated test-structures calibrated with on-wafer TRL. These results are compared against 3D EM simulation of the intrinsic test-structures. To analyze difference between the measured and intrinsic EM simulation results, on-wafer TRL calibration performed on EM simulation results of a dedicated test-structure is also presented.
{"title":"Importance of complete characterization setup on on-wafer TRL calibration in sub-THz range","authors":"C. Yadav, M. Deng, M. De matos, S. Frégonèse, T. Zimmer","doi":"10.1109/ICMTS.2018.8383798","DOIUrl":"https://doi.org/10.1109/ICMTS.2018.8383798","url":null,"abstract":"In this paper, we present the effect of different sub-mm and mm-wave probe geometry and topology on the measurement results of dedicated test-structures calibrated with on-wafer TRL. These results are compared against 3D EM simulation of the intrinsic test-structures. To analyze difference between the measured and intrinsic EM simulation results, on-wafer TRL calibration performed on EM simulation results of a dedicated test-structure is also presented.","PeriodicalId":271839,"journal":{"name":"2018 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121428790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-19DOI: 10.1109/ICMTS.2018.8383757
M. Tadayoni, S. Hariharan, S. Lemke, T. Pate-Cazal, B. Bertello, V. Tiwari, N. Do
Split-gate flash memory technology had recently been used in neuromorphic computation where a non-volatile memory array is designed in such a way that enables high-precision tuning of individual memory elements. This work proposes for the first time a SPICE model of the two-transistor, select gate and floating gate, of the split-gate flash memory cell, implemented in a 180 nm CMOS technology, that allows the users to set the individual memory cell to any precise analog state.
{"title":"Modeling split-gate flash memory cell for advanced neuromorphic computing","authors":"M. Tadayoni, S. Hariharan, S. Lemke, T. Pate-Cazal, B. Bertello, V. Tiwari, N. Do","doi":"10.1109/ICMTS.2018.8383757","DOIUrl":"https://doi.org/10.1109/ICMTS.2018.8383757","url":null,"abstract":"Split-gate flash memory technology had recently been used in neuromorphic computation where a non-volatile memory array is designed in such a way that enables high-precision tuning of individual memory elements. This work proposes for the first time a SPICE model of the two-transistor, select gate and floating gate, of the split-gate flash memory cell, implemented in a 180 nm CMOS technology, that allows the users to set the individual memory cell to any precise analog state.","PeriodicalId":271839,"journal":{"name":"2018 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130265241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-19DOI: 10.1109/ICMTS.2018.8383754
Dale J. McQuirk, Chris R. Baker, Brad Smith
Precision analog circuit accuracy in a microcontroller product was impacted by unmodeled behavior across the temperature range. Three critical analog circuits from the microcontroller were built and tested in discrete parametric test structures. It was shown that a process with reduced parasitic edge FET leakage dramatically improved the accuracy of the analog circuits, which were operating in the subthreshold region.
{"title":"Test structures to evaluate the impact of parasitic edge FET on circuits operating in weak inversion","authors":"Dale J. McQuirk, Chris R. Baker, Brad Smith","doi":"10.1109/ICMTS.2018.8383754","DOIUrl":"https://doi.org/10.1109/ICMTS.2018.8383754","url":null,"abstract":"Precision analog circuit accuracy in a microcontroller product was impacted by unmodeled behavior across the temperature range. Three critical analog circuits from the microcontroller were built and tested in discrete parametric test structures. It was shown that a process with reduced parasitic edge FET leakage dramatically improved the accuracy of the analog circuits, which were operating in the subthreshold region.","PeriodicalId":271839,"journal":{"name":"2018 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116575330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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