Advantage of small geometry silicon MOSFETs for high-frequency analog applications under low power supply voltage of 0.5 V

M. Saito, M. Ono, R. Fujimoto, C. Takahashi, H. Tanimoto, N. Ito, T. Ohguro, T. Yoshitomi, H. Momose, H. Iwai
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引用次数: 10

Abstract

Low noise high-frequency analog operation of small geometry silicon MOSFETs is demonstrated. By scaling gate length down to 0.3-sub 0.1 /spl mu/m regions, excellent low noise figure of 1.5 dB at 2 GHz was obtained with low drain current of 0.3 mA//spl mu/m at f/sub T/ value of 20-65 GHz-the same level as today's high performance silicon bipolar transistors in research level. Even at low voltage operation such as 0.5 V, extremely high cutoff frequency of 48 GHz was realized by sub 0.1 /spl mu/m gate length nMOSFETs. Such low voltage operations allow one order of magnitude smaller power consumption compared with 2 V power supply voltage.
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小几何尺寸硅mosfet的优势,适用于0.5 V低电源电压下的高频模拟应用
演示了小几何尺寸硅mosfet的低噪声高频模拟工作。通过将栅极长度缩小到0.3-sub - 0.1 /spl mu/m区域,在20-65 GHz的f/sub - T/值下,获得了2 GHz时1.5 dB的优异低噪声系数,漏极电流为0.3 mA//spl mu/m,与目前研究水平的高性能硅双极晶体管相同。即使在0.5 V等低电压下,栅极长度小于0.1 /spl mu/m的nmosfet也能实现48 GHz的极高截止频率。与2v电源电压相比,这种低电压操作允许一个数量级的功耗降低。
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Semiconductor CIM system, innovation toward the year 2000 CVD SiN/sub X/ anti-reflective coating for sub-0.5 /spl mu/m lithography Advantage of small geometry silicon MOSFETs for high-frequency analog applications under low power supply voltage of 0.5 V The influence of oxygen at epitaxial Si/Si substrate interface for 0.1 /spl mu/m epitaxial Si channel N-MOSFETs grown by UHV-CVD High-current, small parasitic capacitance MOS FET on a poly-Si interlayered (PSI: /spl Psi/) SOI wafer
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