Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520862
K. Yamashita, H. Nakaoka, K. Kurimoto, H. Umimoto, S. Odanaka
The effect of the gate to drain capacitance on low voltage operated CMOS devices is investigated. It is found that the Miller and feed-forward effects are enhanced with the reduction of the supply voltage. The reduction of the gate overlap capacitance as well as the threshold voltage and junction capacitance is a key issue to achieve high speed circuit operation at low supply voltage. We propose a low power, high speed T-gate CMOS device with dual gate structure using an amorphous-Si/poly-Si layer. A new process scheme is proposed to prevent boron penetration and to fabricate the T-gate structure effectively. It is found that the new T-gate CMOS with dual gate structure reduces the gate to drain overlap capacitance maintaining high current drivability at low power-supply voltage.
{"title":"Impact of the reduction of the gate to drain capacitance on low voltage operated CMOS devices","authors":"K. Yamashita, H. Nakaoka, K. Kurimoto, H. Umimoto, S. Odanaka","doi":"10.1109/VLSIT.1995.520862","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520862","url":null,"abstract":"The effect of the gate to drain capacitance on low voltage operated CMOS devices is investigated. It is found that the Miller and feed-forward effects are enhanced with the reduction of the supply voltage. The reduction of the gate overlap capacitance as well as the threshold voltage and junction capacitance is a key issue to achieve high speed circuit operation at low supply voltage. We propose a low power, high speed T-gate CMOS device with dual gate structure using an amorphous-Si/poly-Si layer. A new process scheme is proposed to prevent boron penetration and to fabricate the T-gate structure effectively. It is found that the new T-gate CMOS with dual gate structure reduces the gate to drain overlap capacitance maintaining high current drivability at low power-supply voltage.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126917142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520885
Y. Sudoh, T. Kaga, J. Yugami, T. Kure
A new isolation with single-Si/sub 3/N/sub 4/-spacer (SSS) OSELO technology is proposed. The features of the SSS OSELO process are low bird's beak penetration and low defect isolation, which are achieved by using low defect-density etching for the Si/sub 3/N/sub 4/ spacer formation, and lower growth-rate and/or a high-temperature oxidation ambient. The SSS OSELO technology allows the 0.15-/spl mu/m low-defect isolation and the fabrication of 1-gigabit DRAM cells.
{"title":"A new SSS-OSELO technology for 0.15-/spl mu/m low-defect isolation","authors":"Y. Sudoh, T. Kaga, J. Yugami, T. Kure","doi":"10.1109/VLSIT.1995.520885","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520885","url":null,"abstract":"A new isolation with single-Si/sub 3/N/sub 4/-spacer (SSS) OSELO technology is proposed. The features of the SSS OSELO process are low bird's beak penetration and low defect isolation, which are achieved by using low defect-density etching for the Si/sub 3/N/sub 4/ spacer formation, and lower growth-rate and/or a high-temperature oxidation ambient. The SSS OSELO technology allows the 0.15-/spl mu/m low-defect isolation and the fabrication of 1-gigabit DRAM cells.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116327316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520844
S.C. Sun, M. Tsai, C. Tsai, H. Chiu
A low-resistivity and low carbon concentration CVD TaN film has been realized by using a new precursor terbutylimido-tris-diethylamido tantalum (TBTDET). Results show that CVD TaN as a diffusion barrier for Cu has higher thermal stability up to 500/spl deg/C than CVD TiN of 450/spl deg/C.
采用新型前驱体叔丁基三乙基氨基钽(TBTDET)制备了一种低电阻率、低碳浓度的CVD TaN薄膜。结果表明，CVD TaN作为Cu的扩散势垒，在500/spl°C时的热稳定性高于CVD TiN (450/spl°C)。
{"title":"Performance of MOCVD tantalum nitride diffusion barrier for copper metallization","authors":"S.C. Sun, M. Tsai, C. Tsai, H. Chiu","doi":"10.1109/VLSIT.1995.520844","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520844","url":null,"abstract":"A low-resistivity and low carbon concentration CVD TaN film has been realized by using a new precursor terbutylimido-tris-diethylamido tantalum (TBTDET). Results show that CVD TaN as a diffusion barrier for Cu has higher thermal stability up to 500/spl deg/C than CVD TiN of 450/spl deg/C.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124575737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520857
T. Furusawa, Y. Homma
A low capacitance multilevel interconnection for high-speed ULSIs is developed. It employs metal-line spaces filled with only a low-dielectric-constant, reflowable organic spin-on glass (SOG). The SOG-filled dielectrics reduce interconnection-capacitance to about 70% that of conventional structures, and provide a breakdown voltage of 1.7 MV/cm. Low via resistance with via holes down to 0.37 /spl mu/m is achieved using O/sub 2/-RIE (reactive ion etching) surface treatment and a W-plug.
{"title":"Low capacitance multilevel interconnection using low-/spl epsi/ organic spin-on glass for quarter-micron high-speed ULSIs","authors":"T. Furusawa, Y. Homma","doi":"10.1109/VLSIT.1995.520857","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520857","url":null,"abstract":"A low capacitance multilevel interconnection for high-speed ULSIs is developed. It employs metal-line spaces filled with only a low-dielectric-constant, reflowable organic spin-on glass (SOG). The SOG-filled dielectrics reduce interconnection-capacitance to about 70% that of conventional structures, and provide a breakdown voltage of 1.7 MV/cm. Low via resistance with via holes down to 0.37 /spl mu/m is achieved using O/sub 2/-RIE (reactive ion etching) surface treatment and a W-plug.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116336876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520893
V. Chen, J. Woo
A novel SDE LBJT on TFSOI substrate has been demonstrated. The fabrication process is self-aligned, with a minimum thermal budget, and is fully compatible with an SOI CMOS process. Good electrical results were obtained. The devices are expected to have good current drive and high frequency performance for low power applications.
{"title":"A low thermal budget, fully self-aligned lateral BJT on thin film SOI substrate for low power BiCMOS applications","authors":"V. Chen, J. Woo","doi":"10.1109/VLSIT.1995.520893","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520893","url":null,"abstract":"A novel SDE LBJT on TFSOI substrate has been demonstrated. The fabrication process is self-aligned, with a minimum thermal budget, and is fully compatible with an SOI CMOS process. Good electrical results were obtained. The devices are expected to have good current drive and high frequency performance for low power applications.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122141575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520854
T. Sugano
Microelectronics is a semi-classical electronics from the viewpoint that the behavior of electrons in devices can be treated with the effective mass approximation and the random phase approximation. On the other hand nanoelectronics is a quantum-mechanical electronics with full use of properties of electron waves, of artificial mini-Brillouin zones, of size dependent energy eigenstate structures and of Coulomb blockade of electron tunneling. New circuit implementation techniques are to be explored in nanoelectronics.
{"title":"Evolution of integrated electronics from microelectronics to nanoelectronics","authors":"T. Sugano","doi":"10.1109/VLSIT.1995.520854","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520854","url":null,"abstract":"Microelectronics is a semi-classical electronics from the viewpoint that the behavior of electrons in devices can be treated with the effective mass approximation and the random phase approximation. On the other hand nanoelectronics is a quantum-mechanical electronics with full use of properties of electron waves, of artificial mini-Brillouin zones, of size dependent energy eigenstate structures and of Coulomb blockade of electron tunneling. New circuit implementation techniques are to be explored in nanoelectronics.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128467877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520836
M. Minami, N. Ohki, H. Ishida, T. Yamanaka, K. Ishibashi, A. Shimizu, T. Kure, T. Nishida, T. Nagano
A high-performance microprocessor-compatible small size full CMOS SRAM cell technology has been developed. A 0.3-/spl mu/m gate length load pMOSFET, formed utilizing amorphous-Si-film through-channel implantation, is merged with a 0.25-/spl mu/m gate length pMOSFET for the peripheral circuits. Mask-free contact for TiN local interconnect is developed with wet etching. A 6.93-/spl mu/m/sup 2/ cell area and a high-performance 1.8-V circuit are thus realized.
{"title":"A 6.93-/spl mu/m/sup 2/ n-gate full CMOS SRAM cell technology with high-performance 1.8-V dual-gate CMOS for peripheral circuits","authors":"M. Minami, N. Ohki, H. Ishida, T. Yamanaka, K. Ishibashi, A. Shimizu, T. Kure, T. Nishida, T. Nagano","doi":"10.1109/VLSIT.1995.520836","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520836","url":null,"abstract":"A high-performance microprocessor-compatible small size full CMOS SRAM cell technology has been developed. A 0.3-/spl mu/m gate length load pMOSFET, formed utilizing amorphous-Si-film through-channel implantation, is merged with a 0.25-/spl mu/m gate length pMOSFET for the peripheral circuits. Mask-free contact for TiN local interconnect is developed with wet etching. A 6.93-/spl mu/m/sup 2/ cell area and a high-performance 1.8-V circuit are thus realized.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130007353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520899
Y. Ohno, T. Kishimoto, K. Sonoda, H. Sayama, S. Komori, A. Kinomura, Y. Horino, K. Fujii, T. Nishimura, M. Takai, H. Miyoshi
The soft-error evaluation method using the nuclear microprobe has been demonstrated. This method realized the quantitative study of the charge collection which induces the soft-error event. The retrograde well structure with the double buried p/sup +/ layers was found to be more effective for the soft-error immunity of DRAMs, as compared with the conventional well structure on the p/sup -/epi/p/sup +/ substrate. These results were well proved by the simulation results. The evaluation method using high-energy nuclear microprobe gives the principle to optimize the well structure for the soft-error immunity of advanced DRAMs.
{"title":"Direct measurement of the soft-error immunity on the DRAM well structure by using the nuclear microprobe","authors":"Y. Ohno, T. Kishimoto, K. Sonoda, H. Sayama, S. Komori, A. Kinomura, Y. Horino, K. Fujii, T. Nishimura, M. Takai, H. Miyoshi","doi":"10.1109/VLSIT.1995.520899","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520899","url":null,"abstract":"The soft-error evaluation method using the nuclear microprobe has been demonstrated. This method realized the quantitative study of the charge collection which induces the soft-error event. The retrograde well structure with the double buried p/sup +/ layers was found to be more effective for the soft-error immunity of DRAMs, as compared with the conventional well structure on the p/sup -/epi/p/sup +/ substrate. These results were well proved by the simulation results. The evaluation method using high-energy nuclear microprobe gives the principle to optimize the well structure for the soft-error immunity of advanced DRAMs.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126219508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520878
S. Chung, S. Cheng, G. Lee, J. Guo
This paper reports a new model and characterization of the reverse short channel effect (RSCE) as result of the lateral nonuniform channel doping profile in submicron MOSFET's. The anomalous increase in the charge pumping current with decreasing channel length has been observed experimentally for the first time by using a charge pumping measurement. This is attributed to the enhanced nonuniform channel doping profile with the decreasing channel length as a result of the interstitial imperfections caused by OED or S/D implant. A simple and accurate model is proposed to determine the effective lateral nonuniform doping profile along the channel. The effective channel doping profile calculated from the new approach presents an obvious doping enhancement near the drain region of submicron devices by comparing with that of long channel devices. The simulated threshold voltages and I-V characteristics based on this profile show excellent agreement with the experimental data.
{"title":"Direct observation of the lateral nonuniform channel doping profile in submicron MOSFET's from an anomalous charge pumping measurement results","authors":"S. Chung, S. Cheng, G. Lee, J. Guo","doi":"10.1109/VLSIT.1995.520878","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520878","url":null,"abstract":"This paper reports a new model and characterization of the reverse short channel effect (RSCE) as result of the lateral nonuniform channel doping profile in submicron MOSFET's. The anomalous increase in the charge pumping current with decreasing channel length has been observed experimentally for the first time by using a charge pumping measurement. This is attributed to the enhanced nonuniform channel doping profile with the decreasing channel length as a result of the interstitial imperfections caused by OED or S/D implant. A simple and accurate model is proposed to determine the effective lateral nonuniform doping profile along the channel. The effective channel doping profile calculated from the new approach presents an obvious doping enhancement near the drain region of submicron devices by comparing with that of long channel devices. The simulated threshold voltages and I-V characteristics based on this profile show excellent agreement with the experimental data.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"374 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115306762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520871
K. Kubota, K. Okuyama, H. Miura, Y. Kawashima, H. Ishizuka, C. Hashimoto
We studied the generation of dislocations during an ESD event by electrothermal and mechanical stress simulations based on analysis of critical mechanical stress for defect formation. We found the local thermal stress by ESD generates dislocations cooperatively with the residual mechanical stress in the Si substrate due to field oxidation. This means that process-induced mechanical stress is another key factor for controlling ESD performance, which will be important especially in low-power applications with severe leak requirements.
{"title":"Effects of process-induced mechanical stress on ESD performance","authors":"K. Kubota, K. Okuyama, H. Miura, Y. Kawashima, H. Ishizuka, C. Hashimoto","doi":"10.1109/VLSIT.1995.520871","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520871","url":null,"abstract":"We studied the generation of dislocations during an ESD event by electrothermal and mechanical stress simulations based on analysis of critical mechanical stress for defect formation. We found the local thermal stress by ESD generates dislocations cooperatively with the residual mechanical stress in the Si substrate due to field oxidation. This means that process-induced mechanical stress is another key factor for controlling ESD performance, which will be important especially in low-power applications with severe leak requirements.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124911090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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