Very large scale integrated circuit architecture performance evaluation using SES modelling tools

Abstract

Very large scale integrated circuits (VLSI) are growing in size, complexity, and circuit density at a very fast pace. There is no limit in the foreseeable future to the amount of intelligence architects would like to see on a single piece of silicon. Technology is keeping good pace with the growing demand of complete "systems" by increasing density. A few million transistors on one chip are already becoming common-place. The development of the architecture of such chips is, however, hampered by the lack of tools. This paper focuses on a very crucial issue, one of confidence in the internal architecture of a VLSI circuit before committing the design to silicon. The SES/Workbench by Scientific and Engineering Software has proven to be a useful tool in early architectural analysis of complex VLSI circuits. The circuit's system level architecture can be modelled fairly quickly to yield results that can save time, money, and resources to design optimum circuits with well understood performance characteristics, without taking recourse to fabricating the chip prototypes. The simulations on the resulting model "run" in reasonable time (million clocks/hr) to provide "on-line" feedback for fine tuning the design.