Unconditionally stable explicit method for the fast 3-D simulation of on-chip power distribution network with through silicon via

Abstract

The equivalent circuit of an on-chip power distribution network (PDN) has a fine 3-D grid structure due to the vias between equipotential conductors, and the vertical couplings between power and ground lines. In addition, a through silicon via is modeled with inductive and capacitive parasitic elements and appended to the PDN. Therefore, the circuit related to the 3-D IC technology tends to be a tightly coupled large network. For the simulation of this type of network, an explicit time marching scheme has an advantage over conventional general-purpose circuit simulators such as SPICE in the computational cost. However, the explicit method has a strict numerical stability condition, which may limit the maximum time step size and increase the total amount of the cost. In this work, we propose the method which is explicit, but stable with no stability condition. Additionally, the proposed unconditionally-stable explicit method is accelerated more by combining with an order reduction technique.