Pub Date : 2013-04-29DOI: 10.1109/ASPDAC.2013.6509646
A. Heittmann, T. Noll
This paper presents a device model for nanoelectronic resistive switches which are based on the electrochemical metallization effect (ECM). The focus is set on modeling variability as well as irreproducibility which are essential properties of scaled nanoelectronic devices. In particular, a Poisson-based random ion deposition model and a non-linear filament surface effect are described. The model is especially useful for circuit simulation and can be implemented on standard circuit simulation platforms such as Spice or Spectre using inbuilt standard elements. Based on this model, effects of variability were examined by Monte Carlo simulation for a particular hybrid CMOS/nanoelectronic circuit. The results show that the proposed model is able to cover significant scaling effects, which is necessary for prospective design space exploration and circuit optimization.
{"title":"Modeling variability and irreproducibility of nanoelectronic resistive switches for circuit simulation","authors":"A. Heittmann, T. Noll","doi":"10.1109/ASPDAC.2013.6509646","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509646","url":null,"abstract":"This paper presents a device model for nanoelectronic resistive switches which are based on the electrochemical metallization effect (ECM). The focus is set on modeling variability as well as irreproducibility which are essential properties of scaled nanoelectronic devices. In particular, a Poisson-based random ion deposition model and a non-linear filament surface effect are described. The model is especially useful for circuit simulation and can be implemented on standard circuit simulation platforms such as Spice or Spectre using inbuilt standard elements. Based on this model, effects of variability were examined by Monte Carlo simulation for a particular hybrid CMOS/nanoelectronic circuit. The results show that the proposed model is able to cover significant scaling effects, which is necessary for prospective design space exploration and circuit optimization.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"236 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114995966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/ASPDAC.2013.6509695
Hongbin Zheng, Qingrui Liu, Junyi Li, Dihu Chen, Zixin Wang
In High-level Synthesis, scheduling has a critical impact on the quality of hardware implementation. However, the schedules of different operations are actually having unequal impacts on the Quality of Result. Based on this fact, we propose a novel scheduling framework, which is able to schedule the operations separately according their significance to Quality of Result, to avoid wasting the computational efforts on noncritical operations. Furthermore, the proposed framework supports global code motion, which helps to improve the speed performance of the hardware implementation by distributing the execution time of operations across the their parent BB.
{"title":"A gradual scheduling framework for problem size reduction and cross basic block parallelism exploitation in high-level synthesis","authors":"Hongbin Zheng, Qingrui Liu, Junyi Li, Dihu Chen, Zixin Wang","doi":"10.1109/ASPDAC.2013.6509695","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509695","url":null,"abstract":"In High-level Synthesis, scheduling has a critical impact on the quality of hardware implementation. However, the schedules of different operations are actually having unequal impacts on the Quality of Result. Based on this fact, we propose a novel scheduling framework, which is able to schedule the operations separately according their significance to Quality of Result, to avoid wasting the computational efforts on noncritical operations. Furthermore, the proposed framework supports global code motion, which helps to improve the speed performance of the hardware implementation by distributing the execution time of operations across the their parent BB.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115604279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/ASPDAC.2013.6509597
W. H. Minhass, P. Pop, J. Madsen, Tsung-Yi Ho
In this paper we are interested in flow-based microfluidic biochips, which are able to integrate the necessary functions for biochemical analysis on-chip. In these chips, the flow of liquid is manipulated using integrated microvalves. By combining several microvalves, more complex units, such as micropumps, mixers, and multiplexers, can be built. In this paper we propose, for the first time to our knowledge, a top-down control synthesis framework for the flow-based biochips. Starting from a given biochemical application and a biochip architecture, we synthesize the control logic that is used by the biochip controller to automatically execute the biochemical application. We also propose a control pin count minimization scheme aimed at efficiently utilizing chip area, reducing macro-assembly around the chip and enhancing chip scalability. We have evaluated our approach using both real-life applications and synthetic benchmarks.
{"title":"Control synthesis for the flow-based microfluidic large-scale integration biochips","authors":"W. H. Minhass, P. Pop, J. Madsen, Tsung-Yi Ho","doi":"10.1109/ASPDAC.2013.6509597","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509597","url":null,"abstract":"In this paper we are interested in flow-based microfluidic biochips, which are able to integrate the necessary functions for biochemical analysis on-chip. In these chips, the flow of liquid is manipulated using integrated microvalves. By combining several microvalves, more complex units, such as micropumps, mixers, and multiplexers, can be built. In this paper we propose, for the first time to our knowledge, a top-down control synthesis framework for the flow-based biochips. Starting from a given biochemical application and a biochip architecture, we synthesize the control logic that is used by the biochip controller to automatically execute the biochemical application. We also propose a control pin count minimization scheme aimed at efficiently utilizing chip area, reducing macro-assembly around the chip and enhancing chip scalability. We have evaluated our approach using both real-life applications and synthetic benchmarks.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124432361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/ASPDAC.2013.6509640
Che-Wei Chang, Jian-Jia Chen, Tei-Wei Kuo, H. Falk
Real-time task scheduling becomes even more challenging with the emerging of island-based multi-core architecture, where the local memory module of an island offers shorter access time than the global memory module does. With such a popular architecture design in mind, this paper exploits real-time task scheduling over island-based homogeneous cores with local and global memory pools. Joint considerations of real-time scheduling and memory allocation are presented to efficiently use the computing and memory resources. A polynomial-time algorithm with an asymptotic 4-approximation bound is proposed to minimize the number of needed islands to successfully schedule tasks. To evaluate the performance of the proposed algorithm, 82 benchmarks from the MRTC, MediaBench, UTDSP, NetBench, and DSPstone benchmark suites were profiled by a worst-case-execution-time analyzer aiT and included in the experiments.
{"title":"Real-time partitioned scheduling on multi-core systems with local and global memories","authors":"Che-Wei Chang, Jian-Jia Chen, Tei-Wei Kuo, H. Falk","doi":"10.1109/ASPDAC.2013.6509640","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509640","url":null,"abstract":"Real-time task scheduling becomes even more challenging with the emerging of island-based multi-core architecture, where the local memory module of an island offers shorter access time than the global memory module does. With such a popular architecture design in mind, this paper exploits real-time task scheduling over island-based homogeneous cores with local and global memory pools. Joint considerations of real-time scheduling and memory allocation are presented to efficiently use the computing and memory resources. A polynomial-time algorithm with an asymptotic 4-approximation bound is proposed to minimize the number of needed islands to successfully schedule tasks. To evaluate the performance of the proposed algorithm, 82 benchmarks from the MRTC, MediaBench, UTDSP, NetBench, and DSPstone benchmark suites were profiled by a worst-case-execution-time analyzer aiT and included in the experiments.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117272144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/ASPDAC.2013.6509662
Bo-Han Zeng, R. Tsay, Ting-Chi Wang
Multi-core system simulation techniques have been especially essential to system development in recent years. Although these techniques have been studied extensively, we have found that both conventional polling and collaborative timing synchronization approaches all encounter a severe scalability issue when the number of target cores is more than that of the host cores. To resolve this issue, we propose an effective hybrid technique that combines the advantage of the two approaches. According to the experimental results, the proposed technique effectively resolves the scalability issue and shows one to four orders of improvement compared to conventional approaches.
{"title":"An efficient hybrid synchronization technique for scalable multi-core instruction set simulations","authors":"Bo-Han Zeng, R. Tsay, Ting-Chi Wang","doi":"10.1109/ASPDAC.2013.6509662","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509662","url":null,"abstract":"Multi-core system simulation techniques have been especially essential to system development in recent years. Although these techniques have been studied extensively, we have found that both conventional polling and collaborative timing synchronization approaches all encounter a severe scalability issue when the number of target cores is more than that of the host cores. To resolve this issue, we propose an effective hybrid technique that combines the advantage of the two approaches. According to the experimental results, the proposed technique effectively resolves the scalability issue and shows one to four orders of improvement compared to conventional approaches.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125804561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/ASPDAC.2013.6509581
K. Yoshioka, A. Shikata, Ryota Sekimoto, T. Kuroda, H. Ishikuro
An extremely low-voltage operating high speed and low power 2bit/step asynchronous SAR ADC is presented. Wide range dynamic threshold configuring comparator is proposed to enable power and area efficient 2bit/step operation. By configuring the comparator threshold by simple Vcm biased current sources, the ADC holds immunity against 10% power supply variation. The prototype ADC fabricated in 40nm CMOS achieved 44.3 dB SNDR with 6.14 MS/s at a single supply voltage of 0.5 V. The ADC achieved a peak FoM of 5.9fJ/conv-step at 0.4V and operates down to 0.35V.
提出了一种超低电压、高速度、低功耗的2位/步异步SAR ADC。提出了宽范围动态阈值配置比较器，实现功率和面积效率的2bit/step操作。通过简单的Vcm偏置电流源配置比较器阈值，ADC对10%的电源变化保持抗扰度。在40nm CMOS中制作的原型ADC在0.5 V单电源电压下以6.14 MS/s的速度实现了44.3 dB SNDR。ADC在0.4V时的峰值FoM为5.9fJ/ convo -step，工作电压降至0.35V。
{"title":"A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADC","authors":"K. Yoshioka, A. Shikata, Ryota Sekimoto, T. Kuroda, H. Ishikuro","doi":"10.1109/ASPDAC.2013.6509581","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509581","url":null,"abstract":"An extremely low-voltage operating high speed and low power 2bit/step asynchronous SAR ADC is presented. Wide range dynamic threshold configuring comparator is proposed to enable power and area efficient 2bit/step operation. By configuring the comparator threshold by simple Vcm biased current sources, the ADC holds immunity against 10% power supply variation. The prototype ADC fabricated in 40nm CMOS achieved 44.3 dB SNDR with 6.14 MS/s at a single supply voltage of 0.5 V. The ADC achieved a peak FoM of 5.9fJ/conv-step at 0.4V and operates down to 0.35V.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"212 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123038230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/ASPDAC.2013.6509588
Chi-Wen Pan, Yu-Min Lee, Pei-Yu Huang, C. Yang, Chang-Tzu Lin, Chia-Hsin Lee, Yung-Fa Chou, D. Kwai
This work presents an iterative look-up table based thermal simulator, I-LUTSim, to efficiently estimate the temperature profile of three-dimensional integrated circuits. I-LUTSim includes two stages. First, the pre-process stage constructs thermal impulse response tables. Then, the simulation stage iteratively calculates the temperature profile via the table lookup. With this two-stage scheme, the maximum absolute error of I-LUTSim is less than 0.41% compared with that of a commercial tool ANSYS. Moreover, I-LUTSim is at least an order of magnitude faster than a fast matrix solver SuperLU [1] for the full-chip temperature simulation.
{"title":"I-LUTSim: An iterative look-up table based thermal simulator for 3-D ICs","authors":"Chi-Wen Pan, Yu-Min Lee, Pei-Yu Huang, C. Yang, Chang-Tzu Lin, Chia-Hsin Lee, Yung-Fa Chou, D. Kwai","doi":"10.1109/ASPDAC.2013.6509588","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509588","url":null,"abstract":"This work presents an iterative look-up table based thermal simulator, I-LUTSim, to efficiently estimate the temperature profile of three-dimensional integrated circuits. I-LUTSim includes two stages. First, the pre-process stage constructs thermal impulse response tables. Then, the simulation stage iteratively calculates the temperature profile via the table lookup. With this two-stage scheme, the maximum absolute error of I-LUTSim is less than 0.41% compared with that of a commercial tool ANSYS. Moreover, I-LUTSim is at least an order of magnitude faster than a fast matrix solver SuperLU [1] for the full-chip temperature simulation.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129822701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/ASPDAC.2013.6509628
Frank Lee, Bill Shen, Willy Chen, Suk Lee
3DIC technology presents a new system integration strategy for the electronics industry to achieve superior system performance with lower power consumption, higher bandwidth, smaller system form factor, and shorter time to market through heterogeneous integration. TSMC's “Chip-on-Wafer-on-Substrate (CoWoS)” technology opens up a new opportunity to bring 3D chip stacking vision from concept to reality. The provided methodology will be discussed about this market trend and the different pieces needed to jointly make it a success, which includes customers' required application, TSMC's support design flow, as well as the ecosystem design enablement of multi-die implementation, DFT solution, thermal analysis, verification and new categories of IPs.
{"title":"3DIC from concept to reality","authors":"Frank Lee, Bill Shen, Willy Chen, Suk Lee","doi":"10.1109/ASPDAC.2013.6509628","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509628","url":null,"abstract":"3DIC technology presents a new system integration strategy for the electronics industry to achieve superior system performance with lower power consumption, higher bandwidth, smaller system form factor, and shorter time to market through heterogeneous integration. TSMC's “Chip-on-Wafer-on-Substrate (CoWoS)” technology opens up a new opportunity to bring 3D chip stacking vision from concept to reality. The provided methodology will be discussed about this market trend and the different pieces needed to jointly make it a success, which includes customers' required application, TSMC's support design flow, as well as the ecosystem design enablement of multi-die implementation, DFT solution, thermal analysis, verification and new categories of IPs.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129303053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/ASPDAC.2013.6509596
Trung Anh Dinh, S. Yamashita, Tsung-Yi Ho, Yuko Hara-Azumi
Microfluidic biochips have been recently proposed to integrate all the necessary functions for biochemical analysis. There are several types of microfluidic biochips; among them there has been a great interest in flow-based microfluidic biochips, in which the flow of liquid is manipulated using integrated microvalves. By combining several microvalves, more complex resource units such as micropumps, switches and mixers can be built. For efficient execution, the flow of liquid routes in microfluidic biochips needs to be scheduled under some resource constraints or routing constraints. The execution time of the biochemical operations depends on the binding and scheduling results. The most previously developed binding and scheduling algorithms are based on heuristics, and there has been no method to obtain optimal results. Considering the above, this paper proposes an optimal method by casting the problem to a clique problem.
{"title":"A clique-based approach to find binding and scheduling result in flow-based microfluidic biochips","authors":"Trung Anh Dinh, S. Yamashita, Tsung-Yi Ho, Yuko Hara-Azumi","doi":"10.1109/ASPDAC.2013.6509596","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509596","url":null,"abstract":"Microfluidic biochips have been recently proposed to integrate all the necessary functions for biochemical analysis. There are several types of microfluidic biochips; among them there has been a great interest in flow-based microfluidic biochips, in which the flow of liquid is manipulated using integrated microvalves. By combining several microvalves, more complex resource units such as micropumps, switches and mixers can be built. For efficient execution, the flow of liquid routes in microfluidic biochips needs to be scheduled under some resource constraints or routing constraints. The execution time of the biochemical operations depends on the binding and scheduling results. The most previously developed binding and scheduling algorithms are based on heuristics, and there has been no method to obtain optimal results. Considering the above, this paper proposes an optimal method by casting the problem to a clique problem.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130522154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/ASPDAC.2013.6509562
Dajiang Zhou, Gang He, Wei Fei, Zhixiang Chen, Jinjia Zhou, S. Goto
An H.264/AVC intra-frame video encoder is implemented in 65nm CMOS. With an efficient intra prediction design, its maximum throughput reaches 1991Mpixels/s for 7680×4320p 60fps video, 9.4x to 32x faster than previous designs. The encoder also incorporates a 1.41Gbins/s CABAC architecture that has been enhanced by 31%. Moreover, low energy consumption is achieved by the high parallelism and hardware efficiency of this design. 1080p 30fps encoding dissipates only 2mW at 0.8V and 9MHz.
{"title":"A 24.5–53.6pJ/pixel 4320p 60fps H.264/AVC intra-frame video encoder chip in 65nm CMOS","authors":"Dajiang Zhou, Gang He, Wei Fei, Zhixiang Chen, Jinjia Zhou, S. Goto","doi":"10.1109/ASPDAC.2013.6509562","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509562","url":null,"abstract":"An H.264/AVC intra-frame video encoder is implemented in 65nm CMOS. With an efficient intra prediction design, its maximum throughput reaches 1991Mpixels/s for 7680×4320p 60fps video, 9.4x to 32x faster than previous designs. The encoder also incorporates a 1.41Gbins/s CABAC architecture that has been enhanced by 31%. Moreover, low energy consumption is achieved by the high parallelism and hardware efficiency of this design. 1080p 30fps encoding dissipates only 2mW at 0.8V and 9MHz.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126709535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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