The CALLAS synthesis system and its application to mechatronic ASIC design problems

P. Windirsch, P. Duzy
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Abstract

The authors demonstrate the use of high-level synthesis for ASIC designs in the mechatronic application domain. The first chip synthesized and fabricated is part of a distance measurement system. Only six weeks were needed for the design of the 2700 equivalent gates ASIC. The hand-crafted standard cell design had taken four times as long for a result of comparable size and performance. Similar results have been obtained in a second ASIC project, which is part of a friction clutch controller.<>
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CALLAS综合系统及其在机电集成电路设计中的应用
作者演示了在机电一体化应用领域中使用高级综合技术进行ASIC设计。第一个合成和制造的芯片是距离测量系统的一部分。设计2700个等效门的ASIC只需要6周时间。手工制作的标准电池设计花费了四倍的时间来获得相当的尺寸和性能。在第二个ASIC项目中也获得了类似的结果,该项目是摩擦离合器控制器的一部分。
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Conditional and unconditional hardware sharing in pipeline synthesis Partitioning strategies within a distributed multilevel logic simulator including dynamic repartitioning Extended 0/1 LP formulation for the scheduling problem in high-level synthesis The CALLAS synthesis system and its application to mechatronic ASIC design problems Realizing expression graphs using table-lookup FPGAs
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