Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410616
Haigeng Wang, N. Dutt, A. Nicolau
The authors present regular schedules, a class of parallel schedules for computing mth-order infinite-impulse response (IIR) filters. These schedules permit the implementation of IIR filters on a family of scalable parallel architectures with varying price/performance characteristics, enabling designers to effectively explore the design space of parallel IIR filter implementations. The technique is illustrated on a target architecture comprising application-specific instruction processors (ASIPs) clustered on multichip modules (MCMs), with the MCMs connected through a scalable interconnection network. The simplicity of the regular schedules facilitates characterization of their interprocessor communications, which makes it possible to generate instruction-level behavior of the design that can be easily mapped onto ASIP architectures. Preliminary results of design space exploration for the fifth-order elliptic wave filter benchmark on the interconnected ASIP architectures are presented.<>
{"title":"Regular schedules for scalable design of IIR filters","authors":"Haigeng Wang, N. Dutt, A. Nicolau","doi":"10.1109/EURDAC.1993.410616","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410616","url":null,"abstract":"The authors present regular schedules, a class of parallel schedules for computing mth-order infinite-impulse response (IIR) filters. These schedules permit the implementation of IIR filters on a family of scalable parallel architectures with varying price/performance characteristics, enabling designers to effectively explore the design space of parallel IIR filter implementations. The technique is illustrated on a target architecture comprising application-specific instruction processors (ASIPs) clustered on multichip modules (MCMs), with the MCMs connected through a scalable interconnection network. The simplicity of the regular schedules facilitates characterization of their interprocessor communications, which makes it possible to generate instruction-level behavior of the design that can be easily mapped onto ASIP architectures. Preliminary results of design space exploration for the fifth-order elliptic wave filter benchmark on the interconnected ASIP architectures are presented.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116707454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410630
P. Gutberlet, W. Rosenstiel
A method is presented to separate the algorithmic specification from the specification of the protocol level allowing a hierarchical design. A VHDL subset and a methodology for the specification is defined. The authors show the target architecture to merge the different levels into one synchronous data path. They present the algorithm especially dealing with the interface part of the specification. Finally, some results are given.<>
{"title":"Interface specification and synthesis for VHDL processes","authors":"P. Gutberlet, W. Rosenstiel","doi":"10.1109/EURDAC.1993.410630","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410630","url":null,"abstract":"A method is presented to separate the algorithmic specification from the specification of the protocol level allowing a hierarchical design. A VHDL subset and a methodology for the specification is defined. The authors show the target architecture to merge the different levels into one synchronous data path. They present the algorithm especially dealing with the interface part of the specification. Finally, some results are given.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124869819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410647
Andrej Magdolen, Jana Bezakova, E. Gramatová, M. Fischerová
The authors describe the functional test generator REGGEN on a register transfer level. The technique of the symbolic simulation was modified by new rules to simplify symbolic expressions. In the REGGEN system a fault simulator at the RT level is also implemented. The efficiency of the REGGEN system has been proved on several gate arrays.<>
{"title":"REGGEN-Test pattern generation on register transfer level","authors":"Andrej Magdolen, Jana Bezakova, E. Gramatová, M. Fischerová","doi":"10.1109/EURDAC.1993.410647","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410647","url":null,"abstract":"The authors describe the functional test generator REGGEN on a register transfer level. The technique of the symbolic simulation was modified by new rules to simplify symbolic expressions. In the REGGEN system a fault simulator at the RT level is also implemented. The efficiency of the REGGEN system has been proved on several gate arrays.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114943052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410642
H. Achatz
An extended zero-one linear programming (O/1 LP) model for the scheduling problem in high-level synthesis is presented. As an extension to former approaches, the 0/1 LP model can handle multifunctional function units as well as different execution times for different instances of the same operation type. These extensions are very important for the applicability of general high-level synthesis tools in real design tasks. The computing time for solving the optimization problems is also acceptable for the new powerful model, since new lower bounds have been introduced that drastically reduce the search space. Some experimental results are shown.<>
{"title":"Extended 0/1 LP formulation for the scheduling problem in high-level synthesis","authors":"H. Achatz","doi":"10.1109/EURDAC.1993.410642","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410642","url":null,"abstract":"An extended zero-one linear programming (O/1 LP) model for the scheduling problem in high-level synthesis is presented. As an extension to former approaches, the 0/1 LP model can handle multifunctional function units as well as different execution times for different instances of the same operation type. These extensions are very important for the applicability of general high-level synthesis tools in real design tasks. The computing time for solving the optimization problems is also acceptable for the new powerful model, since new lower bounds have been introduced that drastically reduce the search space. Some experimental results are shown.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114532251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410680
P. Keresztes, I. Agotai
The authors describe a process with a concurrent control flow as a superprocess. A combined VHDL and data/control flow graph description is proposed so as to create abstract level behavioral specifications containing a concurrent control flow. The functions of the simulation compiler are exposed.<>
{"title":"The concept of superprocesses for high-level synthesis and their VHDL modelling","authors":"P. Keresztes, I. Agotai","doi":"10.1109/EURDAC.1993.410680","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410680","url":null,"abstract":"The authors describe a process with a concurrent control flow as a superprocess. A combined VHDL and data/control flow graph description is proposed so as to create abstract level behavioral specifications containing a concurrent control flow. The functions of the simulation compiler are exposed.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130088638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410617
R. Hermida, Milagros Fernández, F. Tirado, V. Sanchez, P. Ruperez
A new method for dealing with the problem of module selection on unscheduled behavioral descriptions is described. The method is based on the application to partitioning of some results of fuzzy set theory. It inherits, from its theoretical basis, some interesting properties, such as global treatment of similarity among operators, and computational simplicity.<>
{"title":"An approach to module binding by fuzzy partitioning","authors":"R. Hermida, Milagros Fernández, F. Tirado, V. Sanchez, P. Ruperez","doi":"10.1109/EURDAC.1993.410617","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410617","url":null,"abstract":"A new method for dealing with the problem of module selection on unscheduled behavioral descriptions is described. The method is based on the application to partitioning of some results of fuzzy set theory. It inherits, from its theoretical basis, some interesting properties, such as global treatment of similarity among operators, and computational simplicity.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130112423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410640
M. Rullán, F. C. Blom, J. Oliver, C. Ferrer
In CMOS technology there are some faults (opens and shorts) that are hard to detect or even undetectable. For this reason layout level design for testability (LLDFT) rules have been developed. These rules prevent the faults or reduce the appearance probability of them. The purpose of this work is to apply a practical set of LLDFT rules on the cells of the library designed at the Centre Nacional de Microelectronica (CNM) in order to obtain a highly testable cell library. The authors summarize the main results (area overhead and performance degradation) of the application of the LLDFT rules on the cells.<>
{"title":"Layout-level design for testability rules for a CMOS cell library","authors":"M. Rullán, F. C. Blom, J. Oliver, C. Ferrer","doi":"10.1109/EURDAC.1993.410640","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410640","url":null,"abstract":"In CMOS technology there are some faults (opens and shorts) that are hard to detect or even undetectable. For this reason layout level design for testability (LLDFT) rules have been developed. These rules prevent the faults or reduce the appearance probability of them. The purpose of this work is to apply a practical set of LLDFT rules on the cells of the library designed at the Centre Nacional de Microelectronica (CNM) in order to obtain a highly testable cell library. The authors summarize the main results (area overhead and performance degradation) of the application of the LLDFT rules on the cells.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132007881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410668
B. Becker, R. Drechsler, P. Molitor
The authors present data structures and an efficient algorithm realizing efficient performance driven generation of integer adders. The generator is parameterized in n, the operands' bitlength, and t/sub n/, the delay of the addition. It outputs an area minimal n-bit adder of the conditional-sum type with delay /spl les/t/sub n/, if such a circuit exists.<>
{"title":"On the implementation of an efficient performance driven generator for conditional-sum-adders","authors":"B. Becker, R. Drechsler, P. Molitor","doi":"10.1109/EURDAC.1993.410668","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410668","url":null,"abstract":"The authors present data structures and an efficient algorithm realizing efficient performance driven generation of integer adders. The generator is parameterized in n, the operands' bitlength, and t/sub n/, the delay of the addition. It outputs an area minimal n-bit adder of the conditional-sum type with delay /spl les/t/sub n/, if such a circuit exists.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124498031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410628
I. Shagurin, A. Ivanov
Methods for taking account of the redundancy influence on the VLSI yield are developed. Using some fundamental redundancy arrangement methods, the interrelation between parameters of initial units and redundant hardware is discussed. On this basis, the generalized design approach is proposed. It can be adapted to demands of application-specific redundant unit design. Based on this approach the program PRIDE is developed. PRIDE provides automatic yield estimation and supports the redundancy logic design.<>
{"title":"Computer-aided technique for optimal design of defect-tolerant VLSI with built-in redundancy","authors":"I. Shagurin, A. Ivanov","doi":"10.1109/EURDAC.1993.410628","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410628","url":null,"abstract":"Methods for taking account of the redundancy influence on the VLSI yield are developed. Using some fundamental redundancy arrangement methods, the interrelation between parameters of initial units and redundant hardware is discussed. On this basis, the generalized design approach is proposed. It can be adapted to demands of application-specific redundant unit design. Based on this approach the program PRIDE is developed. PRIDE provides automatic yield estimation and supports the redundancy logic design.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122009147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410692
L. Ramachandran, Sanjiv Narayan, F. Vahid, D. Gajski
VHDL procedures and functions greatly increase the power and utility of the language for specifying designs. While these constructs are being used extensively for modeling, most VHDL synthesis tools limit their synthesis to a single implementation style such as treating them as a component. The authors evaluate four techniques for the synthesis of procedures/functions and discuss their relative merits and demerits. They examine these implementation styles in the light of VHDL signals and wait statement semantics. The results of the various implementation styles are shown on several examples.<>
{"title":"Synthesis of functions and procedures in behavioral VHDL","authors":"L. Ramachandran, Sanjiv Narayan, F. Vahid, D. Gajski","doi":"10.1109/EURDAC.1993.410692","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410692","url":null,"abstract":"VHDL procedures and functions greatly increase the power and utility of the language for specifying designs. While these constructs are being used extensively for modeling, most VHDL synthesis tools limit their synthesis to a single implementation style such as treating them as a component. The authors evaluate four techniques for the synthesis of procedures/functions and discuss their relative merits and demerits. They examine these implementation styles in the light of VHDL signals and wait statement semantics. The results of the various implementation styles are shown on several examples.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128497010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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