Residue arithmetic multiplier based on the radix-4 signed-digit multiple-valued arithmetic circuits

Shugang Wei, K. Shimizu
{"title":"Residue arithmetic multiplier based on the radix-4 signed-digit multiple-valued arithmetic circuits","authors":"Shugang Wei, K. Shimizu","doi":"10.1109/ICVD.1999.745150","DOIUrl":null,"url":null,"abstract":"Residue arithmetic multiplier based on the radix-4 signed-digit arithmetic is presented. Conventional residue arithmetic circuits have been designed using binary number arithmetic system, but the carry propagation arises which limits the speed of arithmetic operations in residue modules. In this paper, two radix-4 signed-digit (SD) number representations, (-2,-1,0,1,2) and (-3,-2,-1,0,1,2,3), are introduced. The former is used for the input and output, and the latter for the inner arithmetic circuit of the presented multiplier. So that, by using integers 4/sup P/ and 4/sup P//spl plusmn/1 as moduli of residue number system (RNS), where p is a positive integer, both the partial product generating circuit and the circuit for sum of the partial products in the multiplier can be efficiently constructed based on the SD number representations. The module m addition, m=4/sup P/ or m=4/sup P//spl plusmn/1, can be performed by an SD adder or an end-around-carry SD adder with the multiple-valued circuits and the addition time is independent of the word length of operands. The modulo m multiplier can be compactly constructed using a binary modulo m SD adder tree based on the multiple-valued addition circuits, and consequently the module m multiplication is performed in O(log/sub 2/p) time.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICVD.1999.745150","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7

Abstract

Residue arithmetic multiplier based on the radix-4 signed-digit arithmetic is presented. Conventional residue arithmetic circuits have been designed using binary number arithmetic system, but the carry propagation arises which limits the speed of arithmetic operations in residue modules. In this paper, two radix-4 signed-digit (SD) number representations, (-2,-1,0,1,2) and (-3,-2,-1,0,1,2,3), are introduced. The former is used for the input and output, and the latter for the inner arithmetic circuit of the presented multiplier. So that, by using integers 4/sup P/ and 4/sup P//spl plusmn/1 as moduli of residue number system (RNS), where p is a positive integer, both the partial product generating circuit and the circuit for sum of the partial products in the multiplier can be efficiently constructed based on the SD number representations. The module m addition, m=4/sup P/ or m=4/sup P//spl plusmn/1, can be performed by an SD adder or an end-around-carry SD adder with the multiple-valued circuits and the addition time is independent of the word length of operands. The modulo m multiplier can be compactly constructed using a binary modulo m SD adder tree based on the multiple-valued addition circuits, and consequently the module m multiplication is performed in O(log/sub 2/p) time.
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基于基数-4符号数多值算术电路的残数算术乘法器
提出了基于基数-4符号数算法的残数乘法器。传统的残数运算电路是利用二进制数运算系统设计的,但残数模块中存在进位传播问题,限制了运算速度。本文介绍了(-2,-1,0,1,2)和(-3,-2,-1,0,1,2,3)两个基数-4的符号数表示。前者用于输入和输出,后者用于所述乘法器的内部算术电路。因此,利用整数4/sup P/和4/sup P//spl plusmn/1作为残数系统(RNS)的模,其中P为正整数,可以基于SD数表示有效地构造乘法器中的偏积产生电路和偏积求和电路。模块m加法,m=4/sup P/或m=4/sup P//spl plusmn/1,可以通过SD加法器或端部进位SD加法器与多值电路进行,加法时间与操作数字长无关。模m乘法器可以使用基于多值加法电路的二进制模m SD加法器树紧凑地构造,因此模m乘法在O(log/sub 2/p)时间内完成。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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