Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745143
A. Bhattacharyya, Saudas Dey
Operational Transconductance Amplifiers (OTA) form an integral part of OTA-C filters. The authors have experimented with OTA-C filters for frequency shaping purposes in micropower all-CMOS hearing aids as against conventionally used switched capacitor filters, as switched capacitor filters present problem due to switching noise and require a double polysilicon technology in a low voltage process. The power supply rejection ratio (PSRR) of such filters becomes important in hearing aids, as the negative supply voltage for the OTA is derived from the low voltage battery by the use of a dc to dc converter through capacitor switching where a ripple voltage on supply rail is inherent due to charging and discharging mechanism in the converter circuit. A regulated cascode (RGC) differential stage is used for OTA to increase the linearity of the differential input stage and ensure an acceptable level of CMRR. An important finding that has emerged in the present investigation from the viewpoint of application of OTA-C filters in hearing aids is that PSRR of high pass filter is much higher compared to that in low pass configuration. The results have been validated both by SPICE simulation and measurement of OTA-C filter chips fabricated for hearing aid application.
{"title":"Sub-circuit analysis for power supply rejection ratio in regulated cascode operational transconductance amplifiers and filters","authors":"A. Bhattacharyya, Saudas Dey","doi":"10.1109/ICVD.1999.745143","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745143","url":null,"abstract":"Operational Transconductance Amplifiers (OTA) form an integral part of OTA-C filters. The authors have experimented with OTA-C filters for frequency shaping purposes in micropower all-CMOS hearing aids as against conventionally used switched capacitor filters, as switched capacitor filters present problem due to switching noise and require a double polysilicon technology in a low voltage process. The power supply rejection ratio (PSRR) of such filters becomes important in hearing aids, as the negative supply voltage for the OTA is derived from the low voltage battery by the use of a dc to dc converter through capacitor switching where a ripple voltage on supply rail is inherent due to charging and discharging mechanism in the converter circuit. A regulated cascode (RGC) differential stage is used for OTA to increase the linearity of the differential input stage and ensure an acceptable level of CMRR. An important finding that has emerged in the present investigation from the viewpoint of application of OTA-C filters in hearing aids is that PSRR of high pass filter is much higher compared to that in low pass configuration. The results have been validated both by SPICE simulation and measurement of OTA-C filter chips fabricated for hearing aid application.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126192451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745203
S. Majumder, B. Bhattacharya, V. Agrawal, M. Bushnell
A complete one-to-one characterization of path delay fault testability for a combinational circuit is presented in terms of testability of stuck-at faults in an equivalent unfolded circuit. The unfolded circuit is obtained simply by replicating the cone feeding each internal fanout stem line, thereby making it internally fanout free. Unfolding preserves both functional, and structural characteristics of the original circuit. Earlier results describing correlation of path delay and stuck-at faults are either incomplete, or use a complex model of equivalent circuit based on timing parameters. We show that a path delay fault (rising or falling) is testable if certain single or multiple stuck-at fault in the equivalent circuit is testable. Thus, all aspects of path delay faults related to testability under various classification schemes are interpreted using the stuck-at fault model alone in the unfolded circuit. The results unify most of the existing concepts, provide a better understanding of path delay faults in logic circuits, and have potential applications in identification of false paths.
{"title":"A complete characterization of path delay faults through stuck-at faults","authors":"S. Majumder, B. Bhattacharya, V. Agrawal, M. Bushnell","doi":"10.1109/ICVD.1999.745203","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745203","url":null,"abstract":"A complete one-to-one characterization of path delay fault testability for a combinational circuit is presented in terms of testability of stuck-at faults in an equivalent unfolded circuit. The unfolded circuit is obtained simply by replicating the cone feeding each internal fanout stem line, thereby making it internally fanout free. Unfolding preserves both functional, and structural characteristics of the original circuit. Earlier results describing correlation of path delay and stuck-at faults are either incomplete, or use a complex model of equivalent circuit based on timing parameters. We show that a path delay fault (rising or falling) is testable if certain single or multiple stuck-at fault in the equivalent circuit is testable. Thus, all aspects of path delay faults related to testability under various classification schemes are interpreted using the stuck-at fault model alone in the unfolded circuit. The results unify most of the existing concepts, provide a better understanding of path delay faults in logic circuits, and have potential applications in identification of false paths.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122385245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745217
A. Kahng, S. Muddu
We describe an improved iterationless approach for computing the effective capacitance of an interconnect load at a driving gate output. The speed and accuracy of our approach makes it suitable for the analysis loop within performance-driven iterative layout optimization. We present an iterationless approach for computing the effective capacitance of an interconnect load at a gate output when the slew time is non-zero (i.e., a ramp). We then extend this effective capacitance algorithm to complex gates, i.e., channel-connected components. Preliminary experimental results using the new effective capacitance approach show that the resulting delay estimates are quite accurate-within 15% of HSPICE-computed delays on data taken from a recent microprocessor design in 0.25 /spl mu/m CMOS technology. The improved driver model reduces the cell delay calculation errors to below 10%; this indicates that accurate modeling of effective capacitance is no longer the dominant source of errors in cell delay calculation.
{"title":"Improved effective capacitance computations for use in logic and layout optimization","authors":"A. Kahng, S. Muddu","doi":"10.1109/ICVD.1999.745217","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745217","url":null,"abstract":"We describe an improved iterationless approach for computing the effective capacitance of an interconnect load at a driving gate output. The speed and accuracy of our approach makes it suitable for the analysis loop within performance-driven iterative layout optimization. We present an iterationless approach for computing the effective capacitance of an interconnect load at a gate output when the slew time is non-zero (i.e., a ramp). We then extend this effective capacitance algorithm to complex gates, i.e., channel-connected components. Preliminary experimental results using the new effective capacitance approach show that the resulting delay estimates are quite accurate-within 15% of HSPICE-computed delays on data taken from a recent microprocessor design in 0.25 /spl mu/m CMOS technology. The improved driver model reduces the cell delay calculation errors to below 10%; this indicates that accurate modeling of effective capacitance is no longer the dominant source of errors in cell delay calculation.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114277925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745219
N. Dhanwada, A. Núñez-Aldana, R. Vemuri
In this paper, we present a technique for characterizing CMOS analog circuits based on directed intervals. The technique consists of an analog performance estimator and a characterization table generator. This characterization information may be efficiently used by the constraint transformation step in an analog synthesis system. We present a genetic algorithm based constraint transformation method, that exploits problem structure by using the circuit characterization information. We discuss the design of the genetic operators that capture the characteristics of the constraint transformation problem. The constraint transformation method that uses the characterization information was compared against one using a conventional genetic algorithm and the experimental results obtained demonstrate the effectiveness of the proposed approach.
{"title":"Component characterization and constraint transformation based on directed intervals for analog synthesis","authors":"N. Dhanwada, A. Núñez-Aldana, R. Vemuri","doi":"10.1109/ICVD.1999.745219","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745219","url":null,"abstract":"In this paper, we present a technique for characterizing CMOS analog circuits based on directed intervals. The technique consists of an analog performance estimator and a characterization table generator. This characterization information may be efficiently used by the constraint transformation step in an analog synthesis system. We present a genetic algorithm based constraint transformation method, that exploits problem structure by using the circuit characterization information. We discuss the design of the genetic operators that capture the characteristics of the constraint transformation problem. The constraint transformation method that uses the characterization information was compared against one using a conventional genetic algorithm and the experimental results obtained demonstrate the effectiveness of the proposed approach.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129572453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745160
B. Courtois, J. Karam, S. Mir, M. Lubaszewski, V. Székely, M. Rencz, K. Hofmann, M. Glesner
This paper deals with design, simulation and test of MEMS (microelectromechanical systems). Both existing tools and open research areas are addressed. An appropriate Computer-Aided Design (CAD) environment is presented. Similarities between the present development of MEMS and the development of microelectronics decades ago are pointed out, including the migration from point tools to CAD frameworks, testing and intellectual property (IP) issues.
{"title":"Design and test of MEMS","authors":"B. Courtois, J. Karam, S. Mir, M. Lubaszewski, V. Székely, M. Rencz, K. Hofmann, M. Glesner","doi":"10.1109/ICVD.1999.745160","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745160","url":null,"abstract":"This paper deals with design, simulation and test of MEMS (microelectromechanical systems). Both existing tools and open research areas are addressed. An appropriate Computer-Aided Design (CAD) environment is presented. Similarities between the present development of MEMS and the development of microelectronics decades ago are pointed out, including the migration from point tools to CAD frameworks, testing and intellectual property (IP) issues.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130281396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745189
Prashant Saxena, P. Pan, C. Liu
Previous approaches to the retiming of latch-based circuits have used the different phases of the clock to prevent race conditions. However, such an approach is not applicable to single-phase clocked circuits. Consequently there is no practical formulation that retimes single-phase clocked circuits containing latches optimally. We present a novel ILP formulation for the retiming of such circuits, along with efficient algorithms to generate its constraint set. This formulation can be used to optimize any criterion whose quality depends on the latch positions and that can be expressed as a linear objective function. As examples, we discuss the optimization of the clock period and the latch count. For the latter we describe a graph transformation to linearize the max-based objective function. Our experiments demonstrate that our formulation is efficient and generates ILPs that are easy to solve.
{"title":"The retiming of single-phase clocked circuits containing level-sensitive latches","authors":"Prashant Saxena, P. Pan, C. Liu","doi":"10.1109/ICVD.1999.745189","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745189","url":null,"abstract":"Previous approaches to the retiming of latch-based circuits have used the different phases of the clock to prevent race conditions. However, such an approach is not applicable to single-phase clocked circuits. Consequently there is no practical formulation that retimes single-phase clocked circuits containing latches optimally. We present a novel ILP formulation for the retiming of such circuits, along with efficient algorithms to generate its constraint set. This formulation can be used to optimize any criterion whose quality depends on the latch positions and that can be expressed as a linear objective function. As examples, we discuss the optimization of the clock period and the latch count. For the latter we describe a graph transformation to linearize the max-based objective function. Our experiments demonstrate that our formulation is efficient and generates ILPs that are easy to solve.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121578028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745119
B. Pain, Guang Yang, B. Olson, T. Shaw, M. Ortiz, J. Heynssens, C. Wrigley, Charlie Ho
The advent of high performance imaging in CMOS technology using active pixel sensors has enabled ultra-low power, miniature, integrated, single-chip camera systems. We report the first fully digital, programmable, 5-wire, large format (512/spl times/512) digital-camera-on-a-chip that integrates the imager array, control logic, ADC, and bias generation on the same chip. The VLSI chip runs off a single (3.3 V) power supply, consumes only 8 mW at video rates, is capable of electronic panning, and produces high quality images with 78 dB dynamic range.
{"title":"A low-power digital camera-on-a-chip implemented in CMOS active pixel approach","authors":"B. Pain, Guang Yang, B. Olson, T. Shaw, M. Ortiz, J. Heynssens, C. Wrigley, Charlie Ho","doi":"10.1109/ICVD.1999.745119","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745119","url":null,"abstract":"The advent of high performance imaging in CMOS technology using active pixel sensors has enabled ultra-low power, miniature, integrated, single-chip camera systems. We report the first fully digital, programmable, 5-wire, large format (512/spl times/512) digital-camera-on-a-chip that integrates the imager array, control logic, ADC, and bias generation on the same chip. The VLSI chip runs off a single (3.3 V) power supply, consumes only 8 mW at video rates, is capable of electronic panning, and produces high quality images with 78 dB dynamic range.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125242523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745173
P. Chauhan, P. Dasgupta, P. Chakrabarti
We present two techniques for compaction of ROBDDs. The first technique extracts isomorphic subtrees from a characteristic function ROBDD (cfBDD), replaces them by multi-output nodes, and stores the extracted subtrees as MTBDDs. The second technique searches pre-defined topological structures (signatures) within the cfBDD and replaces them by multi-output nodes. While both approaches are able to extract isomporphic subtrees in the cfBDD, the signature scanning approach gives a significantly better compression and reduces the simulation time as compared to cfBDD simulation, which shows that is possible to compress BDDs and yet simulate them faster.
{"title":"Exploiting isomorphism for compaction and faster simulation of binary decision diagrams","authors":"P. Chauhan, P. Dasgupta, P. Chakrabarti","doi":"10.1109/ICVD.1999.745173","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745173","url":null,"abstract":"We present two techniques for compaction of ROBDDs. The first technique extracts isomorphic subtrees from a characteristic function ROBDD (cfBDD), replaces them by multi-output nodes, and stores the extracted subtrees as MTBDDs. The second technique searches pre-defined topological structures (signatures) within the cfBDD and replaces them by multi-output nodes. While both approaches are able to extract isomporphic subtrees in the cfBDD, the signature scanning approach gives a significantly better compression and reduces the simulation time as compared to cfBDD simulation, which shows that is possible to compress BDDs and yet simulate them faster.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127790017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745179
M. Mahesh, Satrajit Gupta, M. Mehendale
Residue Number System based applications involve modulo-arithmetic which is typically implemented using look-up-tables (LUTs) for a small value of modulus. In this paper we present a data coding technique to minimize the area of these LUTs when implemented using two level logic structures such as PLAs. We also present a technique that exploits the symmetry in these computations to further optimize the LUTs. Results show that area improvement of upto 66% can be achieved using these techniques.
{"title":"Improving area efficiency of residue number system based implementation of DSP algorithms","authors":"M. Mahesh, Satrajit Gupta, M. Mehendale","doi":"10.1109/ICVD.1999.745179","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745179","url":null,"abstract":"Residue Number System based applications involve modulo-arithmetic which is typically implemented using look-up-tables (LUTs) for a small value of modulus. In this paper we present a data coding technique to minimize the area of these LUTs when implemented using two level logic structures such as PLAs. We also present a technique that exploits the symmetry in these computations to further optimize the LUTs. Results show that area improvement of upto 66% can be achieved using these techniques.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133789598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745201
N. Menezes, C. C. Chen
Recently Lillis, et al. (see Proc. Custom Integrated Conf., p. 259-262, May 1995) presented an elegant dynamic programming approach to RC interconnect delay optimization through driver sizing, repeater insertion, and, wire sizing which employs the Elmore delay model for RC delay estimation and a crude repeater delay model. This approach, however, ignores an equally important aspect of interconnect optimization: transition time constraints at the sinks. More importantly, Elmore delay techniques because of their inherent inaccuracy are not suited to spec-based design which is directed towards synthesizing nets with user-specified delay/transition time requirements at the sinks. In this paper we present techniques for delay and transition time optimization for RC nets in the context of accurate moment-matching techniques for computing the RC delays and transition times, and an accurate driver/repeater delay model. The asymptotic increase in runtime over the Elmore delay model is O(q/sup 2/) where q is the order of the moment-matching approximation. Experiments on industrial nets indicate that this increase in runtime is acceptable. Our algorithm yields delay and transition time estimates within 5% of circuit simulation results.
最近，Lillis等人(见Proc. Custom Integrated Conf.， p. 259-262, 1995年5月)提出了一种优雅的动态规划方法，通过驱动器尺寸、中继器插入和电线尺寸来优化RC互连延迟，该方法采用Elmore延迟模型进行RC延迟估计和粗糙的中继器延迟模型。然而，这种方法忽略了互连优化的一个同样重要的方面:汇合点的转换时间限制。更重要的是，Elmore延迟技术由于其固有的不准确性而不适合基于规范的设计，这种设计旨在综合具有用户指定的延迟/转换时间要求的网络。在本文中，我们在计算RC延迟和过渡时间的精确矩匹配技术以及精确的驱动器/中继器延迟模型的背景下，提出了RC网络的延迟和过渡时间优化技术。Elmore延迟模型的运行时间渐近增长为O(q/sup 2/)，其中q是矩匹配近似的阶数。在工业网络上的实验表明，这种运行时间的增加是可以接受的。我们的算法产生的延迟和过渡时间估计在电路仿真结果的5%以内。
{"title":"Spec-based repeater insertion and wire sizing for on-chip interconnect","authors":"N. Menezes, C. C. Chen","doi":"10.1109/ICVD.1999.745201","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745201","url":null,"abstract":"Recently Lillis, et al. (see Proc. Custom Integrated Conf., p. 259-262, May 1995) presented an elegant dynamic programming approach to RC interconnect delay optimization through driver sizing, repeater insertion, and, wire sizing which employs the Elmore delay model for RC delay estimation and a crude repeater delay model. This approach, however, ignores an equally important aspect of interconnect optimization: transition time constraints at the sinks. More importantly, Elmore delay techniques because of their inherent inaccuracy are not suited to spec-based design which is directed towards synthesizing nets with user-specified delay/transition time requirements at the sinks. In this paper we present techniques for delay and transition time optimization for RC nets in the context of accurate moment-matching techniques for computing the RC delays and transition times, and an accurate driver/repeater delay model. The asymptotic increase in runtime over the Elmore delay model is O(q/sup 2/) where q is the order of the moment-matching approximation. Experiments on industrial nets indicate that this increase in runtime is acceptable. Our algorithm yields delay and transition time estimates within 5% of circuit simulation results.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124383862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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