Effect of SSN-induced PDN noise on a LVDS output buffer

Abstract

As the semiconductor nanotechnology process progresses, advanced devices achieve high performance by reducing parasitic effects, including logic variations caused by noise at SSN input and outputs (I/O), and output bufferpsilas timing variations caused by switching I/O banks (SSN-TV). This paper presents these timing variations by studying the LVDS output jitter of a 65-nm wire-bond FPGA device in the presence of SSN. By using differential signaling, the effect of inductive coupling can be significantly reduced, allowing the PDN effect to be observed more clearly. Due to the PDN resonance effect, the LVDS output jitter reaches maximum (peak) when the transient current in the PDN oscillates at the resonance frequency. This study shows that output jitter peaks not only when the SSN is at the resonance frequency but also when it is at half the resonance frequency.