Latch-up in FinFET technologies

Abstract

Low-power FinFET technologies pose new challenges for latch-up safe design. Downscaling of the feature size causes significant drop of the trigger current and holding voltage in the latch-up (LU) victims (standard-cell logic). It is accompanied by an increase of resistance in the wells and tap-connections. The increase of well resistance causes a drop in the efficiency of latch-up guard-rings around aggressors (diffusion at IO). Weak victims and inefficient guard-rings boost the latch-up hazard in FinFET, compared to a planar process. New strategies for latch-up safe design are described.