A 200 MHz 100 K ECL output buffer for CMOS ASICs

Third Annual IEEE Proceedings on ASIC Seminar and Exhibit Pub Date : 1990-09-17 DOI:10.1109/ASIC.1990.186147

T. Gabara, D. Thompson

引用次数: 7

Abstract

The operation and design of 200-MHz 100 K ECL output buffers for CMOS ASICs are described. It is shown how the components of the buffer output driver transistor, gate voltage generator, and low skew input drivers are combined into unique clock and data output buffers. A section on unity gain op-amp design describes how a number of these buffers are used on an ASIC. Application guidelines (curves) to illustrate the tradeoff between the buffer frequency and the number of buffers on an ASIC application are presented. The advantages that this input buffer provides in the area of low ground bounce generation is presented. Waveforms from an ASIC with 24 balanced and 16 single ended ECL output buffers are presented.<>

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用于CMOS asic的200mhz 100k ECL输出缓冲器

介绍了用于CMOS专用集成电路的200 mhz 100k ECL输出缓冲器的工作原理和设计。它显示了如何将缓冲输出驱动器晶体管，栅极电压发生器和低倾斜输入驱动器的组件组合成独特的时钟和数据输出缓冲器。关于单位增益运算放大器设计的一节描述了如何在ASIC上使用这些缓冲器。应用指南(曲线)，以说明缓冲频率之间的权衡和缓冲的ASIC应用程序的数量。介绍了该输入缓冲器在低地面弹跳产生方面的优点。给出了具有24个平衡和16个单端ECL输出缓冲器的ASIC的波形。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Third Annual IEEE Proceedings on ASIC Seminar and Exhibit

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