Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186159
A. Rucinski
Diverse ASIC programs have been established in more than 100 universities across the United States. In most schools, however, the focus is placed on full-custom VLSI rather than semicustom VLSI design. An emerging infrastructure in VLSI seems to favor the first of the two mentioned design styles. A familiarization with these types of rapid prototyping by the prospective electrical engineers is an important issue in education. A treatment of this issue is presented.<>
{"title":"Rapid prototyping, is there an educational dilemma? (ASIC design)","authors":"A. Rucinski","doi":"10.1109/ASIC.1990.186159","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186159","url":null,"abstract":"Diverse ASIC programs have been established in more than 100 universities across the United States. In most schools, however, the focus is placed on full-custom VLSI rather than semicustom VLSI design. An emerging infrastructure in VLSI seems to favor the first of the two mentioned design styles. A familiarization with these types of rapid prototyping by the prospective electrical engineers is an important issue in education. A treatment of this issue is presented.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115404754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186120
Y. Chu, Yih-June Liou, Jong-Leih Chen
After partitioning the circuit into a set of clock groups, an event-driven approach is used to find paths with delays greater than a given threshold value. False paths detected during event propagation are reported to the user. In addition to breaking asynchronous loops dynamically, the tool also checks setup/hold time and minimum pulse width violations in a multiple clock environment. Experimental results are shown to demonstrated the efficiency and effectiveness of the proposed algorithms.<>
{"title":"Efficient timing analysis for general synchronous and asynchronous circuits","authors":"Y. Chu, Yih-June Liou, Jong-Leih Chen","doi":"10.1109/ASIC.1990.186120","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186120","url":null,"abstract":"After partitioning the circuit into a set of clock groups, an event-driven approach is used to find paths with delays greater than a given threshold value. False paths detected during event propagation are reported to the user. In addition to breaking asynchronous loops dynamically, the tool also checks setup/hold time and minimum pulse width violations in a multiple clock environment. Experimental results are shown to demonstrated the efficiency and effectiveness of the proposed algorithms.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116985838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186165
M. Chian, K.S. Eshbaugh, L. Sanders
CAE tools for use in design of bipolar analog ICS with the analog FASTRACK design system are discussed. Two tools, device design and autogen, automatically design and lay out a full-custom transistor. The statistical analysis and modeling (SAM) tool is used to generate model parameter values for a variety of deterministic and statistical simulation modes. A tool for automated synthesis of IC macromodels (ASIM) is provided to create macro/behavioral models of analog and digital blocks for up to 100 times faster circuit-level simulation.<>
{"title":"Automated CAE tools for full custom design of bipolar analog ASICs","authors":"M. Chian, K.S. Eshbaugh, L. Sanders","doi":"10.1109/ASIC.1990.186165","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186165","url":null,"abstract":"CAE tools for use in design of bipolar analog ICS with the analog FASTRACK design system are discussed. Two tools, device design and autogen, automatically design and lay out a full-custom transistor. The statistical analysis and modeling (SAM) tool is used to generate model parameter values for a variety of deterministic and statistical simulation modes. A tool for automated synthesis of IC macromodels (ASIM) is provided to create macro/behavioral models of analog and digital blocks for up to 100 times faster circuit-level simulation.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114160615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186106
J. Drummond, M. Lepkowski
An advanced submicron BiCMOS process and an ASIC memory compiler are discussed. The BICMOS process uses bipolar transistors to enhance the fast CMOS transistors by driving heavily loaded nodes at high speeds. The multiple layers of metal in the process significantly increase the gate density available for system-level design.<>
{"title":"BiCMOS submicron compiler memories","authors":"J. Drummond, M. Lepkowski","doi":"10.1109/ASIC.1990.186106","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186106","url":null,"abstract":"An advanced submicron BiCMOS process and an ASIC memory compiler are discussed. The BICMOS process uses bipolar transistors to enhance the fast CMOS transistors by driving heavily loaded nodes at high speeds. The multiple layers of metal in the process significantly increase the gate density available for system-level design.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128763263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186083
T. Vucurevich, R. Bowman
Summary form only given. Modeling methods that are commonly employed by designers in abstracting mixed signal circuit behavior are discussed. Modeling and overall simulation methods for both analog and digital sections of the circuit that can significantly reduce the total simulation time (CPU and designer) while maintaining acceptable accuracy are also considered.<>
{"title":"Modeling and simulation methods for mixed signal circuit simulation","authors":"T. Vucurevich, R. Bowman","doi":"10.1109/ASIC.1990.186083","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186083","url":null,"abstract":"Summary form only given. Modeling methods that are commonly employed by designers in abstracting mixed signal circuit behavior are discussed. Modeling and overall simulation methods for both analog and digital sections of the circuit that can significantly reduce the total simulation time (CPU and designer) while maintaining acceptable accuracy are also considered.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129194771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186100
M. S. Young
The activities of the design team formed for development of a follow-on machine to the Sparcstation 1 are discussed. The design team partitioned the design into four chips: the cache controller (CACHE+), memory management unit (MMU+), direct memory access (DMA+), and dynamic memory controller (RAM+). Architectural changes and higher integration eliminated two of the ASICs used on the Sparcstation 1 and dropped the usage of one of the ASICs from two to one part per board. One ASIC, a video controller, was reused. The manpower requirements of the project and the design/verification tools used by the design team are discussed.<>
{"title":"ASIC design in a next generation workstation","authors":"M. S. Young","doi":"10.1109/ASIC.1990.186100","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186100","url":null,"abstract":"The activities of the design team formed for development of a follow-on machine to the Sparcstation 1 are discussed. The design team partitioned the design into four chips: the cache controller (CACHE+), memory management unit (MMU+), direct memory access (DMA+), and dynamic memory controller (RAM+). Architectural changes and higher integration eliminated two of the ASICs used on the Sparcstation 1 and dropped the usage of one of the ASICs from two to one part per board. One ASIC, a video controller, was reused. The manpower requirements of the project and the design/verification tools used by the design team are discussed.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132300094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186107
P. Mukherjee
The design of an efficient content-addressable memory (CAM) where the search operation can be based on any one of the following functions: equality, greater than, less than, greater than or equal to, and less than or equal to, is discussed. This design gives the user the flexibility to choose any one function, or multiple functions with minimum increase in gate complexity, thus making it suitable for use in an ASIC environment.<>
{"title":"An efficient ASIC design of a content-addressable memory (CAM)","authors":"P. Mukherjee","doi":"10.1109/ASIC.1990.186107","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186107","url":null,"abstract":"The design of an efficient content-addressable memory (CAM) where the search operation can be based on any one of the following functions: equality, greater than, less than, greater than or equal to, and less than or equal to, is discussed. This design gives the user the flexibility to choose any one function, or multiple functions with minimum increase in gate complexity, thus making it suitable for use in an ASIC environment.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133461038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186172
P.L. Schartow
It is shown how an automatic characterization and modeling system called the library compiler reduces library development time, produces a consistent methodology, and increases the accuracy of characterization and modeling. The major characteristics of the system that help produce library development are shown to be automatic input vector generation, process portability, hierarchical parameters, CPU efficiency, timing window specification, and hierarchical characterization. These characteristics provide a flexibility for the ASIC designer. This flexibility mixed with the consistent reliability and maintainability of the software offers a degree of confidence in the characterization and modeling data of the libraries.<>
{"title":"Automatic characterization and modeling (ASIC design)","authors":"P.L. Schartow","doi":"10.1109/ASIC.1990.186172","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186172","url":null,"abstract":"It is shown how an automatic characterization and modeling system called the library compiler reduces library development time, produces a consistent methodology, and increases the accuracy of characterization and modeling. The major characteristics of the system that help produce library development are shown to be automatic input vector generation, process portability, hierarchical parameters, CPU efficiency, timing window specification, and hierarchical characterization. These characteristics provide a flexibility for the ASIC designer. This flexibility mixed with the consistent reliability and maintainability of the software offers a degree of confidence in the characterization and modeling data of the libraries.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123451296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186085
J.A. Machado
It is pointed out that MAX+PLUS software is the ideal tool to produce a prototype efficiently, completely, and quickly. It provides all necessary prototyping tools in one single system, ensuring that necessary iterations do not slow down the overall prototyping process. Furthermore, the MAX family of EPLDs provides high-density, high-performance devices that integrate general-purpose logic designs. With the integration potential in excess of 100 TTL packages, a single MAX EPLD can incorporate a large design on a single chip. Teaming the MAX family of EPLDs with MAX+PLUS design software to rapidly create functioning prototypes saves design time, thereby reducing the time to market, ultimately producing more profits for a company.<>
{"title":"Putting the designer in control with desktop prototyping","authors":"J.A. Machado","doi":"10.1109/ASIC.1990.186085","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186085","url":null,"abstract":"It is pointed out that MAX+PLUS software is the ideal tool to produce a prototype efficiently, completely, and quickly. It provides all necessary prototyping tools in one single system, ensuring that necessary iterations do not slow down the overall prototyping process. Furthermore, the MAX family of EPLDs provides high-density, high-performance devices that integrate general-purpose logic designs. With the integration potential in excess of 100 TTL packages, a single MAX EPLD can incorporate a large design on a single chip. Teaming the MAX family of EPLDs with MAX+PLUS design software to rapidly create functioning prototypes saves design time, thereby reducing the time to market, ultimately producing more profits for a company.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128921591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186089
K. E. Dubowski
Partitioning considerations for systems that contain digital, analog, and memory components are discussed. Optimal partitioning requires consideration of the product features and performance, market size and share of that market, the product life cycle, system price, system cost, and manufacturing capability. The system specification should quantify each of these items. The system specification is a guide for partitioning the system. The optimal partitioning meets all system specifications at the lowest total system cost.<>
{"title":"Partitioning systems into ASICs","authors":"K. E. Dubowski","doi":"10.1109/ASIC.1990.186089","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186089","url":null,"abstract":"Partitioning considerations for systems that contain digital, analog, and memory components are discussed. Optimal partitioning requires consideration of the product features and performance, market size and share of that market, the product life cycle, system price, system cost, and manufacturing capability. The system specification should quantify each of these items. The system specification is a guide for partitioning the system. The optimal partitioning meets all system specifications at the lowest total system cost.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"107 Pt 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129096387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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