Appendix A2: Use of Verilog HDL and Logisim to FSM

Abstract

© 2021 John Wiley & Sons Ltd. Published 2021 by John Wiley & Sons Ltd. Companion website: www.wiley.com/go/minns/digitalsystemdesign This appendix describes FSM models in Verilog code and then simulates them using the SynaptiCAD VeriLogger Extreme system and the Logisim gate level simulator. It also provides an explanation to the workings of the Verilog HDL language used to describe the structure and operation of the FSM to help the reader’s understanding. It then looks at how to use the Logisim logic simulator. This is very handy to use to simulate most FSM systems and can complement the development process a great deal. Let’s start with the use of the Verilog HDL system and the use of SynaptiCAD. The SynaptiCAD software can be downloaded from htpp://www.syncad.com/ syn_down.html or Google Synapticad.co.uk, search for SynaptiCAD Tools for the Thinking Mind. This is designed to work with Microsoft Windows. You can, of course, use the MAC computer with Parallels and Window 10. A more detailed account of Verilog HDL is provided in Chapters 6–8 in Minns and Elliott (2008). These three chapters can be purchased from Wiley at a separate cost (much lower than the total cost of the book). Also, the same book is available in the IET library. This new book looks at Verilog HDL as it progresses. Following this approach, the reader can learn much. The book covers a lot of the design methods used at the end of Chapters 3, 4, 5, and 7 as well as Appendix A2, A3, A4, A5, and A6.