Digital System Design using FSMs最新文献

英文中文

Introduction to Finite State Machines 有限状态机导论

Digital System Design using FSMs

Pub Date : 2021-06-25 DOI: 10.1002/9781119782735.ch1

David Dobor

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Introduction to FSM Synthesis FSM综合介绍

Digital System Design using FSMs

Pub Date : 2021-06-25 DOI: 10.1002/9781119782735.ch3

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Appendix A3: Counters, Shift Registers, Input, and Output with an FSM 附录A3:计数器、移位寄存器、FSM的输入和输出

Digital System Design using FSMs

Pub Date : 2021-06-25 DOI: 10.1002/9781119782735.app3

© 2021 John Wiley & Sons Ltd. Published 2021 by John Wiley & Sons Ltd. Companion website: www.wiley.com/go/minns/digitalsystemdesign This appendix contains a number of techniques to help in the development of synchronous binary counters and shift registers. These are used in some of the designs covered in various chapters throughout this book. There is also an example of the memory tester FSM using the Logisim Simulator.

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Appendix A2: Use of Verilog HDL and Logisim to FSM 附录A2:使用Verilog HDL和Logisim到FSM

Digital System Design using FSMs

Pub Date : 2021-06-25 DOI: 10.1002/9781119782735.app2

© 2021 John Wiley & Sons Ltd. Published 2021 by John Wiley & Sons Ltd. Companion website: www.wiley.com/go/minns/digitalsystemdesign This appendix describes FSM models in Verilog code and then simulates them using the SynaptiCAD VeriLogger Extreme system and the Logisim gate level simulator. It also provides an explanation to the workings of the Verilog HDL language used to describe the structure and operation of the FSM to help the reader’s understanding. It then looks at how to use the Logisim logic simulator. This is very handy to use to simulate most FSM systems and can complement the development process a great deal. Let’s start with the use of the Verilog HDL system and the use of SynaptiCAD. The SynaptiCAD software can be downloaded from htpp://www.syncad.com/ syn_down.html or Google Synapticad.co.uk, search for SynaptiCAD Tools for the Thinking Mind. This is designed to work with Microsoft Windows. You can, of course, use the MAC computer with Parallels and Window 10. A more detailed account of Verilog HDL is provided in Chapters 6–8 in Minns and Elliott (2008). These three chapters can be purchased from Wiley at a separate cost (much lower than the total cost of the book). Also, the same book is available in the IET library. This new book looks at Verilog HDL as it progresses. Following this approach, the reader can learn much. The book covers a lot of the design methods used at the end of Chapters 3, 4, 5, and 7 as well as Appendix A2, A3, A4, A5, and A6.

©2021 John Wiley & Sons Ltd2021年由John Wiley & Sons Ltd出版。配套网站:www.wiley.com/go/minns/digitalsystemdesign本附录用Verilog代码描述FSM模型，然后使用SynaptiCAD VeriLogger Extreme系统和Logisim门级模拟器进行仿真。它还解释了用于描述FSM的结构和操作的Verilog HDL语言的工作原理，以帮助读者理解。然后介绍如何使用Logisim逻辑模拟器。这对于模拟大多数FSM系统非常方便，并且可以极大地补充开发过程。让我们从Verilog HDL系统和SynaptiCAD的使用开始。SynaptiCAD软件下载路径:http://www.syncad.com/ syn_down.html或Google SynaptiCAD .co。uk，搜索SynaptiCAD工具的思维思维。这是为微软Windows设计的。当然，你可以在MAC电脑上安装Parallels和windows 10。Minns和Elliott(2008)的第6-8章提供了Verilog HDL的更详细说明。这三章可以从Wiley单独购买(远低于书的总成本)。同样的书也可以在IET库中找到。这本新书着眼于Verilog HDL的进展。按照这种方法，读者可以学到很多东西。本书在第3、4、5和7章以及附录A2、A3、A4、A5和A6的末尾介绍了很多设计方法。

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Appendix A6: The Rotational Detector Using Logisim Simulator with Sub‐Circuits 附录A6:使用带子电路的逻辑模拟器的旋转检测器

Digital System Design using FSMs

Pub Date : 2021-06-25 DOI: 10.1002/9781119782735.app6

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Appendix A1: Boolean Algebra 附录A1:布尔代数

Digital System Design using FSMs

Pub Date : 2021-06-25 DOI: 10.1002/9781119782735.app1

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Index 指数

Digital System Design using FSMs

Pub Date : 2021-06-25 DOI: 10.1002/9781119782735.index

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Further Event‐Driven FSM Design 进一步的事件驱动FSM设计

Digital System Design using FSMs

Pub Date : 2021-06-25 DOI: 10.1002/9781119782735.ch6

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Using FSMs to Control External Devices 通过FSMs控制外部设备

Digital System Design using FSMs

Pub Date : 2021-06-25 DOI: 10.1002/9781119782735.ch2

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Appendix A4: Finite State Machines Using Verilog Behavioural Mode 附录A4:使用Verilog行为模式的有限状态机

Digital System Design using FSMs

Pub Date : 2021-06-25 DOI: 10.1002/9781119782735.app4

In this book finite state machines (FSMs) have been implemented using the equations obtained from the state diagram/Petri net. This approach ensures that the logic for the state machine is under complete control of the designer. However, if the state machine is implemented using behavioural mode, the Verilog compiler will optimize the design. Remember that the behavioural method describes the behaviour of the designed system. There is a very close relationship between the state diagram and the behavioural Verilog description that allows a direct translation from the state diagram to the Verilog code.

在这本书中，有限状态机(FSMs)已经实现使用从状态图/Petri网获得的方程。这种方法确保了状态机的逻辑完全处于设计人员的控制之下。但是，如果使用行为模式实现状态机，Verilog编译器将优化设计。记住，行为方法描述的是所设计系统的行为。状态图和Verilog行为描述之间存在非常密切的关系，这允许从状态图直接转换为Verilog代码。

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