All-digital skew-tolerant interfacing method for systems with rational frequency ratios among Multiple Clock Domains: Leveraging a priori timing information

Abstract

As deep sub-micron (DSM) technology improves, the need for interfacing modules in multiple clock domains (MCD) is increasing. This work proposes a novel interfacing method for point-to-point communication between modules whose frequencies are rationally related. The introduction of two stages of FIFO-like interfacing registers makes this method skew tolerant. It also allows a slower module to receive or transmit safely data to or from a faster module without slowing down the frequency of the faster module, which is a quality that is required for serializers and deserializers. A complete functional validation of the proposed interfacing method is performed using RTL-level simulation.