Double-Gate FDSOI Based SRAM Bitcell Circuit Designs with Different Back-Gate Biasing Configurations

Abstract

Power saving techniques have become essential for modern digital systems. Large on-chip SRAM memories are used in these systems and therefore it is necessary to optimize SRAM bitcell circuit to minimize the power consumption. In addition to this, it is equally important to design SRAM cell with high reliability and stability. Power gating technique with sleep transistor if applied to SRAM cell will degrade the performance of the cell. In this paper, Fully Depleted Silicon-on-Insulator (FDSOI) device based SRAM designs are proposed which eliminate the requirement of sleep transistors to reduce the power consumption. This reduces overall complexity and overheads of power gating memory designs. Based on this approach seven SRAM bitcell configurations are presented in the paper. Performance metrics of different SRAM configurations are evaluated and compared in HSPICE.