Dongyu Li, Zhijie Chen, Xu Liu, Zhiqi Shen, Y. Xing, Peiyuan Wan
{"title":"Digital Decimation Filter Design for a 3rd-Order Sigma-Delta Modulator with Achieving 129 dB SNR","authors":"Dongyu Li, Zhijie Chen, Xu Liu, Zhiqi Shen, Y. Xing, Peiyuan Wan","doi":"10.1109/asid52932.2021.9651718","DOIUrl":null,"url":null,"abstract":"A digital decimation filter in a 3rd-order Sigma-Delta analog-to-digital converter (Σ-Δ ADC) is proposed in this paper. The digital filter consists of a cascaded integrator comb (CIC) filter, a compensation filter, a half-band filter, and a configurable decimation multiple module. CSD coding is used and the FIR filter structure is optimized in this paper to greatly reduce the area of the multiplier and the number of registers. The decimation factor can be configured from 512 to 4096, and the signal-to-noise ratio (SNR) performance increases with higher decimation factor. Cooperating with a 3rd-order 1-bit modulator, this design can achieve 129dB SNR with a 512 decimation factor. Simulation results shows that this design has realized the complete function of the digital sampling filter with configurable sampling multiples.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/asid52932.2021.9651718","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A digital decimation filter in a 3rd-order Sigma-Delta analog-to-digital converter (Σ-Δ ADC) is proposed in this paper. The digital filter consists of a cascaded integrator comb (CIC) filter, a compensation filter, a half-band filter, and a configurable decimation multiple module. CSD coding is used and the FIR filter structure is optimized in this paper to greatly reduce the area of the multiplier and the number of registers. The decimation factor can be configured from 512 to 4096, and the signal-to-noise ratio (SNR) performance increases with higher decimation factor. Cooperating with a 3rd-order 1-bit modulator, this design can achieve 129dB SNR with a 512 decimation factor. Simulation results shows that this design has realized the complete function of the digital sampling filter with configurable sampling multiples.
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