Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651713
Wenqiang Yang, Lunyao Wang, Kailei Li
Approximate computing is a design way that sacrifices certain accuracy in exchange for circuit performance. The purpose is to reduce the circuit area, delay and power dissipation. In this paper, an approximate adder design method for Ripple Carry Adder (RCA) is proposed. The method mainly consists of three parts: (1) Building a library of inexact full adders with the parameters of error characteristic and area. (2) Using genetic algorithm to choose different approximate full adders for multi-bits RCAs under error distance constraints. (3) Error distance calculation by disjoint sharp product operation with logic cover. Compared with accurate RCA, the circuit area optimization of multi-bits approximate adder proposed in this paper can reach 36.21% when the mean error distance and normalized error distance are less than 1%.
{"title":"An Approximate Adder Design Based on Inexact Full Adders","authors":"Wenqiang Yang, Lunyao Wang, Kailei Li","doi":"10.1109/asid52932.2021.9651713","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651713","url":null,"abstract":"Approximate computing is a design way that sacrifices certain accuracy in exchange for circuit performance. The purpose is to reduce the circuit area, delay and power dissipation. In this paper, an approximate adder design method for Ripple Carry Adder (RCA) is proposed. The method mainly consists of three parts: (1) Building a library of inexact full adders with the parameters of error characteristic and area. (2) Using genetic algorithm to choose different approximate full adders for multi-bits RCAs under error distance constraints. (3) Error distance calculation by disjoint sharp product operation with logic cover. Compared with accurate RCA, the circuit area optimization of multi-bits approximate adder proposed in this paper can reach 36.21% when the mean error distance and normalized error distance are less than 1%.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114136005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651683
Zhiqiang Xu, Zhu Liang, Ziheng Zhou, Zhenmin Li, Gaoming Du, Xiaolei Wang, Yuanyuan Song
Ultra wide band (UWB) technology is widely used in indoor three-dimensional positioning system because of its wide bandwidth advantage and outstanding anti-narrow band interference ability. However, the high cost of base stations limit widespread use of UWB technology. At present, mainstream UWB positioning algorithms need to use four base stations, and the calculation process is complex. This paper proposes a three-base-station UWB location algorithm based on TOF (time of flight). The proposed algorithm also simplify the calculation procedure of 3D positioning, using three base stations, which effectviely reduces the cost of adoption for UWB 3D positioning system.
{"title":"A Precise 3D Positioning Approach Based on UWB with Reduced Base Stations","authors":"Zhiqiang Xu, Zhu Liang, Ziheng Zhou, Zhenmin Li, Gaoming Du, Xiaolei Wang, Yuanyuan Song","doi":"10.1109/asid52932.2021.9651683","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651683","url":null,"abstract":"Ultra wide band (UWB) technology is widely used in indoor three-dimensional positioning system because of its wide bandwidth advantage and outstanding anti-narrow band interference ability. However, the high cost of base stations limit widespread use of UWB technology. At present, mainstream UWB positioning algorithms need to use four base stations, and the calculation process is complex. This paper proposes a three-base-station UWB location algorithm based on TOF (time of flight). The proposed algorithm also simplify the calculation procedure of 3D positioning, using three base stations, which effectviely reduces the cost of adoption for UWB 3D positioning system.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114614979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651490
Guangxian Dong, Yalin Zheng, Shan He, Donghui Guo, Lin Li
With the development of integrated circuits, more and more transistors are integrated on one chip, and the more complex circuit structure on the chip increases the difficulty of the design. Therefore, it becomes important to automatically identify specific circuit modules from the netlist of a large-scale circuit. Subcircuit identification is essential in the applications for function verification, Layout versus Schematic (LVS) and logic synthesis in reverse engineering. In this paper, the topology feature expression of circuit structure is optimized for complex circuit detection in integrated circuits. Based on the fast subgraph isomorphism algorithm, the circuit identification with high accuracy and low computational complexity is realized. The efficiency of this method is verified by the experiments of subcircuit recognition in different scale circuits.
{"title":"Subcircuit Identification Method Based on Subgraph Isomorphism","authors":"Guangxian Dong, Yalin Zheng, Shan He, Donghui Guo, Lin Li","doi":"10.1109/asid52932.2021.9651490","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651490","url":null,"abstract":"With the development of integrated circuits, more and more transistors are integrated on one chip, and the more complex circuit structure on the chip increases the difficulty of the design. Therefore, it becomes important to automatically identify specific circuit modules from the netlist of a large-scale circuit. Subcircuit identification is essential in the applications for function verification, Layout versus Schematic (LVS) and logic synthesis in reverse engineering. In this paper, the topology feature expression of circuit structure is optimized for complex circuit detection in integrated circuits. Based on the fast subgraph isomorphism algorithm, the circuit identification with high accuracy and low computational complexity is realized. The efficiency of this method is verified by the experiments of subcircuit recognition in different scale circuits.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121682618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Evolutionary circuit is an important part of electronic design automation. It is a kind of automatic circuit design system by intelligent algorithm, widely used in robot controller design, circuit design and other fields. Compared with other intelligent algorithms, Particle Swarm Optimization (PSO) has better performance in the process of circuit evolution, but it has the disadvantage of falling into local optimum easily during evolution, resulting in meaningless increase of computing resources. This paper proposes a hybrid algorithm based on Ising model and PSO algorithm for optimizing combinational logic circuits. The Ising model is a kind of stochastic process model describing the material phase transition and has the property that it can accept a worse solution than the current one with a certain probability, which can increase the diversity of particles and avoid particles trapped in local optima point during the evolutionary process. Experimental results show that the hybrid algorithm has better performance in terms of computational complexity and circuit area.
{"title":"Design of Combinational Digital Circuits Optimized with Ising Model and PSO Algorithm","authors":"Ying Li, Penglei Zhao, Bingrui Guo, Chenhui Zhao, Xiaojie Liu, Shan He, Donghui Guo","doi":"10.1109/asid52932.2021.9651723","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651723","url":null,"abstract":"Evolutionary circuit is an important part of electronic design automation. It is a kind of automatic circuit design system by intelligent algorithm, widely used in robot controller design, circuit design and other fields. Compared with other intelligent algorithms, Particle Swarm Optimization (PSO) has better performance in the process of circuit evolution, but it has the disadvantage of falling into local optimum easily during evolution, resulting in meaningless increase of computing resources. This paper proposes a hybrid algorithm based on Ising model and PSO algorithm for optimizing combinational logic circuits. The Ising model is a kind of stochastic process model describing the material phase transition and has the property that it can accept a worse solution than the current one with a certain probability, which can increase the diversity of particles and avoid particles trapped in local optima point during the evolutionary process. Experimental results show that the hybrid algorithm has better performance in terms of computational complexity and circuit area.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130016745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651676
Nan Jiang, Ping Lin, Yulong He, Zhuozhi Tan, Jin Hu
In order to solve the problem that the computing power of processors in the post-Moore era cannot keep up with the speed of daily data generation, improve the ability of data retrieval and replacement, and ensure practicability, we learn from previous research and switch from traditional software to hardware to achieve regular matching. Based on the regular expression of the road characteristic, a regular matching hardware engine architecture is proposed and designed. Using RAM characteristics in this circuit, through different input configurations, there is no need to re-modify the circuit in the FPGA, so that it can achieve different pattern matching functions. It solves part of the generality problems caused by the diversity of modes, and satisfies common scenarios that require dynamic update of matching rules. And all matching processes are completed by only one basic core, saving a lot of logic resources. The processing speed is roughly 1 clock and 1 cycle to process 1 byte, which is close to the processing limit of digital circuits for single-byte data streams. Finally, the circuit is analyzed and compared with the circuit performance of typical research in the past, and the research work in the future is prospected.
{"title":"Design of A New Type of Regular Expression Matching Engine Based on FPGA","authors":"Nan Jiang, Ping Lin, Yulong He, Zhuozhi Tan, Jin Hu","doi":"10.1109/asid52932.2021.9651676","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651676","url":null,"abstract":"In order to solve the problem that the computing power of processors in the post-Moore era cannot keep up with the speed of daily data generation, improve the ability of data retrieval and replacement, and ensure practicability, we learn from previous research and switch from traditional software to hardware to achieve regular matching. Based on the regular expression of the road characteristic, a regular matching hardware engine architecture is proposed and designed. Using RAM characteristics in this circuit, through different input configurations, there is no need to re-modify the circuit in the FPGA, so that it can achieve different pattern matching functions. It solves part of the generality problems caused by the diversity of modes, and satisfies common scenarios that require dynamic update of matching rules. And all matching processes are completed by only one basic core, saving a lot of logic resources. The processing speed is roughly 1 clock and 1 cycle to process 1 byte, which is close to the processing limit of digital circuits for single-byte data streams. Finally, the circuit is analyzed and compared with the circuit performance of typical research in the past, and the research work in the future is prospected.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130457378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651680
Zheng Wang, Xu Liu, Peiyuan Wan, Zhijie Chen
This paper presents a Successive Approximation Register/Single Slope (SAR/SS) two-step hybrid Analog-to-Digital Converter (ADC) circuit for sensor arrays. A 10-bit column-parallel SAR/SS ADC architecture with the area and speed performances compromise is proposed. A 6-bit SAR ADC performs the coarse quantization in the first step, and a SS ADC further performs the 4-bit fine quantization in the second step to complete the final data conversion. The ADC circuit is designed in TSMC 0.18 μm CMOS process with the 1.8 V power supply voltage. A sampling rate of 1 Msps is achieved at the clock frequency of 25 MHz, and the power consumption per channel is only 127.26 μW. The Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) of the ADC are -0.375 LSB/+0.375 LSB and - 0.375 LSB/+1.5 LSB, respectively. The Effective Number of Bits (ENOB) and Signal-to-Noise Ratio (SNR) are 9.44 bit and 60.49 dB, respectively. A Figure of Merit (FOM) of 183.22 fJ/conv is achieved.
{"title":"Design of a column-parallel SAR/SS two-step hybrid ADC for sensor arrays","authors":"Zheng Wang, Xu Liu, Peiyuan Wan, Zhijie Chen","doi":"10.1109/asid52932.2021.9651680","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651680","url":null,"abstract":"This paper presents a Successive Approximation Register/Single Slope (SAR/SS) two-step hybrid Analog-to-Digital Converter (ADC) circuit for sensor arrays. A 10-bit column-parallel SAR/SS ADC architecture with the area and speed performances compromise is proposed. A 6-bit SAR ADC performs the coarse quantization in the first step, and a SS ADC further performs the 4-bit fine quantization in the second step to complete the final data conversion. The ADC circuit is designed in TSMC 0.18 μm CMOS process with the 1.8 V power supply voltage. A sampling rate of 1 Msps is achieved at the clock frequency of 25 MHz, and the power consumption per channel is only 127.26 μW. The Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) of the ADC are -0.375 LSB/+0.375 LSB and - 0.375 LSB/+1.5 LSB, respectively. The Effective Number of Bits (ENOB) and Signal-to-Noise Ratio (SNR) are 9.44 bit and 60.49 dB, respectively. A Figure of Merit (FOM) of 183.22 fJ/conv is achieved.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126576263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651488
Ying-Yi Chu, Shao-Hui Shieh, Hai Feng, Hanyong Deng, M. Shiau, Der-Chen Huang
A Sarry-Select Adder (CSA) strikes a proper balance between the time delay and area occupation for advanced adder designs. This paper presents a transistor-level circuit implementation of a high-speed CSA, and covers the following design issues: (1) a row of Multiplexer (MUX) is reconfigured in such a way as to increase its operating speed, (2) a conventional add-one circuit is improved to reduce the transistor count, and to eliminate the threshold voltage drop, and (3) a quantity is defined to optimize the block sizes for long word length numbers. Fabricated using TSMC 90-nm CMOS technology, the proposed and a number of published CSAs are simulated for 8, 16, 32 and 64-bit word lengths to validate the performance superiority of this work. In the 64-bit case, the proposed CSA provides an up to 42.1% delay reduction, a 26.1% power reduction, a 57.3% Power-Delay Product (PDP) reduction and a 28.7% transistor count reduction relative to a conventional counterpart.
{"title":"A High-Speed Carry-Select Adder with Optimized Block Sizes","authors":"Ying-Yi Chu, Shao-Hui Shieh, Hai Feng, Hanyong Deng, M. Shiau, Der-Chen Huang","doi":"10.1109/asid52932.2021.9651488","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651488","url":null,"abstract":"A Sarry-Select Adder (CSA) strikes a proper balance between the time delay and area occupation for advanced adder designs. This paper presents a transistor-level circuit implementation of a high-speed CSA, and covers the following design issues: (1) a row of Multiplexer (MUX) is reconfigured in such a way as to increase its operating speed, (2) a conventional add-one circuit is improved to reduce the transistor count, and to eliminate the threshold voltage drop, and (3) a quantity is defined to optimize the block sizes for long word length numbers. Fabricated using TSMC 90-nm CMOS technology, the proposed and a number of published CSAs are simulated for 8, 16, 32 and 64-bit word lengths to validate the performance superiority of this work. In the 64-bit case, the proposed CSA provides an up to 42.1% delay reduction, a 26.1% power reduction, a 57.3% Power-Delay Product (PDP) reduction and a 28.7% transistor count reduction relative to a conventional counterpart.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122057698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651710
Xiangxiang Wei, Gaoming Du, Xiaolei Wang, Hongfang Cao, Shijie Hu, Duoli Zhang, Zhenmin Li
Image edge is considered to be the most important attribute to provide valuable image perception information. At present, video image data is developing towards high resolution and high frame number. The image data processing capacity is huge, so the processing speed is very strict to meet the real-time performance of image data transmission. In this context, we present a method to accelerate the real-time video image edge detection. FPGA is used as the development platform. The real-time edge detection algorithm of image data with 1280x720 resolution and 30 frame/s, combined with median filter, Sobel edge detection algorithm and corrosion expansion algorithm, makes the running time of image processing module shorter. The color image of the video image collected by camera is processed. The HDMI interface shows that the scheme has achieved ideal results in the FPGA hardware platform simulation model, greatly improves the efficiency of the algorithm, and provides a guarantee for the speed and stability of the real-time image processing system.
{"title":"FPGA Implementation of Hardware Accelerator for Real-time Video Image Edge Detection","authors":"Xiangxiang Wei, Gaoming Du, Xiaolei Wang, Hongfang Cao, Shijie Hu, Duoli Zhang, Zhenmin Li","doi":"10.1109/asid52932.2021.9651710","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651710","url":null,"abstract":"Image edge is considered to be the most important attribute to provide valuable image perception information. At present, video image data is developing towards high resolution and high frame number. The image data processing capacity is huge, so the processing speed is very strict to meet the real-time performance of image data transmission. In this context, we present a method to accelerate the real-time video image edge detection. FPGA is used as the development platform. The real-time edge detection algorithm of image data with 1280x720 resolution and 30 frame/s, combined with median filter, Sobel edge detection algorithm and corrosion expansion algorithm, makes the running time of image processing module shorter. The color image of the video image collected by camera is processed. The HDMI interface shows that the scheme has achieved ideal results in the FPGA hardware platform simulation model, greatly improves the efficiency of the algorithm, and provides a guarantee for the speed and stability of the real-time image processing system.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129385641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651684
Jeni Liao, Jianxiong Yang, Kangling, Minjuan Zheng, M. Shiau, Hong-Chong Wu, Ching-Hwa Cheng, Don-Gey Liu
In this paper, a low-voltage current-mode instrumentation amplifier (IA) will be investigated. The main structure consists of two Operational Floating Current Conveyors (OFCCs) with a high-pass filter, low-pass filter, and the chopping technique to filter out noises. The OFCC was designed to operate in the current mode that can perform all the functions of an operational amplifier in an instrumentation amplifier at low voltages. A single power supply set at 1.2V to reduce the power consumption was designed in our study. Some of the MOSFETs were designed to operate in the subthreshold region to reduce the power of the circuit. And a self-cascode structure was employed to enhance its tracking capability at the output. In our simulation, the TSMC 0.18μm CMOS technology was used for our OFCC. According to the results, the IA can perform to achieve 99 dB for common mode rejection ratio (CMRR) with a 10 kHz bandwidth. It is highly feasible to realize a low-power wearable electronic device with our IA.
{"title":"Design of a Low-Voltage Instrumentation Amplifier at 1.2 V","authors":"Jeni Liao, Jianxiong Yang, Kangling, Minjuan Zheng, M. Shiau, Hong-Chong Wu, Ching-Hwa Cheng, Don-Gey Liu","doi":"10.1109/asid52932.2021.9651684","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651684","url":null,"abstract":"In this paper, a low-voltage current-mode instrumentation amplifier (IA) will be investigated. The main structure consists of two Operational Floating Current Conveyors (OFCCs) with a high-pass filter, low-pass filter, and the chopping technique to filter out noises. The OFCC was designed to operate in the current mode that can perform all the functions of an operational amplifier in an instrumentation amplifier at low voltages. A single power supply set at 1.2V to reduce the power consumption was designed in our study. Some of the MOSFETs were designed to operate in the subthreshold region to reduce the power of the circuit. And a self-cascode structure was employed to enhance its tracking capability at the output. In our simulation, the TSMC 0.18μm CMOS technology was used for our OFCC. According to the results, the IA can perform to achieve 99 dB for common mode rejection ratio (CMRR) with a 10 kHz bandwidth. It is highly feasible to realize a low-power wearable electronic device with our IA.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131302385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651726
Tianxiang Xu, Ping Li, Xiao-xi Wang
This paper aims to establish an intelligent diagnosis model of cervical cancer screening and to solve the shortcomings of the physician and traditional computer-aided diagnosis methods in the current. We propose a computer-aided diagnosis method based on transfer learning, which uses the pre-trained MobileNetV2 model to classify colposcopic images. Firstly, the data is augmented and normalized, and then the MobileNetV2 model pre-trained on ImageNet is used to realize the classification diagnosis of cervical lesions in colposcopic images. Finally, the diagnosis results are compared with those of colposcopic physicians. Experiments show that this method can effectively diagnose CIN2+ lesions with an accuracy rate of 75.00%, which is higher than the average level of diagnosis by colposcopy physicians. This method overcomes the shortcomings of physicians’ diagnoses to a certain extent. The efficiency of CIN2+ lesion classification for colposcopy images is superior to other mainstream models, which is greatly significant for the current cervical lesion screening.
{"title":"Cervical Lesions Classification Based on Pre-trained MobileNet Model","authors":"Tianxiang Xu, Ping Li, Xiao-xi Wang","doi":"10.1109/asid52932.2021.9651726","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651726","url":null,"abstract":"This paper aims to establish an intelligent diagnosis model of cervical cancer screening and to solve the shortcomings of the physician and traditional computer-aided diagnosis methods in the current. We propose a computer-aided diagnosis method based on transfer learning, which uses the pre-trained MobileNetV2 model to classify colposcopic images. Firstly, the data is augmented and normalized, and then the MobileNetV2 model pre-trained on ImageNet is used to realize the classification diagnosis of cervical lesions in colposcopic images. Finally, the diagnosis results are compared with those of colposcopic physicians. Experiments show that this method can effectively diagnose CIN2+ lesions with an accuracy rate of 75.00%, which is higher than the average level of diagnosis by colposcopy physicians. This method overcomes the shortcomings of physicians’ diagnoses to a certain extent. The efficiency of CIN2+ lesion classification for colposcopy images is superior to other mainstream models, which is greatly significant for the current cervical lesion screening.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124178740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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