{"title":"NTX: A 260 Gflop/sW Streaming Accelerator for Oblivious Floating-Point Algorithms in 22 nm FD-SOI","authors":"Fabian Schuiki, Michael Schaffner, L. Benini","doi":"10.1109/ISOCC47750.2019.9078495","DOIUrl":null,"url":null,"abstract":"In this work we present the first complete design, silicon implementation and measurements in 22 nm FD-SOI of the Network Training Accelerator (NTX) architectural concept [1]. NTX is based on a newly designed partial carrysave \"wide-inside\" (300 bit) fused multiply-accumulate (FMAC) unit ensuring IEEE 754 compliance and a Root Mean Squared Error 1.7_lower than a conventional 32 bit FPU on long accumulations such as dot products and convolutions.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISOCC47750.2019.9078495","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract
In this work we present the first complete design, silicon implementation and measurements in 22 nm FD-SOI of the Network Training Accelerator (NTX) architectural concept [1]. NTX is based on a newly designed partial carrysave "wide-inside" (300 bit) fused multiply-accumulate (FMAC) unit ensuring IEEE 754 compliance and a Root Mean Squared Error 1.7_lower than a conventional 32 bit FPU on long accumulations such as dot products and convolutions.
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