Pub Date : 2019-10-06DOI: 10.1109/ISOCC47750.2019.9078518
Fu‐Xing Liu, Xiao-Yu Zhang, C. Quan, Jong‐Chul Lee
In this paper, a new dual-band Wilkinson power divider (PD) featuring simple structure, miniaturized size, and high design flexibility is presented, whose function is mainly realized by a novel dual-band biasing network (DBN). Compared to the conventional one, the half-wavelength transmission lines (TLs) are replaced by zero-degree composite right- and lefthanded (CRLH) TLs, which configuration results in a compact size, and high design flexibility that different with the previous CRLH-TL based dual-band studies, the impedance of the utilized CRLH-TL can be freely selected. Meanwhile, closed-form design equations are derived and can be mathematically utilized to introduce a large number of passbands. For demonstration, a dual-band Wilkinson PD centered at 1.90 GHz and 2.45 GHz is designed and fabricated. It is worth noting that the two frequencies are chosen so that the first frequency is for LTE mobile communication, while the other band is for wireless fidelity (WIFI), Bluetooth, etc. Good agreement between the theoretical and experimental results can be observed. Besides the low in-band insertion loss and full-ports matching properties, the proposed PD also features a good out-of-band rejection performance.
{"title":"Zero-Degree TL Based Dual-Band Wilkinson Power Divider for Multi-Band Wireless Applications","authors":"Fu‐Xing Liu, Xiao-Yu Zhang, C. Quan, Jong‐Chul Lee","doi":"10.1109/ISOCC47750.2019.9078518","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078518","url":null,"abstract":"In this paper, a new dual-band Wilkinson power divider (PD) featuring simple structure, miniaturized size, and high design flexibility is presented, whose function is mainly realized by a novel dual-band biasing network (DBN). Compared to the conventional one, the half-wavelength transmission lines (TLs) are replaced by zero-degree composite right- and lefthanded (CRLH) TLs, which configuration results in a compact size, and high design flexibility that different with the previous CRLH-TL based dual-band studies, the impedance of the utilized CRLH-TL can be freely selected. Meanwhile, closed-form design equations are derived and can be mathematically utilized to introduce a large number of passbands. For demonstration, a dual-band Wilkinson PD centered at 1.90 GHz and 2.45 GHz is designed and fabricated. It is worth noting that the two frequencies are chosen so that the first frequency is for LTE mobile communication, while the other band is for wireless fidelity (WIFI), Bluetooth, etc. Good agreement between the theoretical and experimental results can be observed. Besides the low in-band insertion loss and full-ports matching properties, the proposed PD also features a good out-of-band rejection performance.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127510271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-06DOI: 10.1109/ISOCC47750.2019.9078494
Young-woo Lee, Youngkwang Lee, Minho Moon, Sungho Kang
The security-related information can be easily leaked by the invasive attacks including micro-probing, which can be potential threats. To prevent the targeted critical information from being leaked by the probe attempt, the secure shield as a protective layer is used on the topmost metal layer. The countermeasure method for detecting the micro-probing is usually conducted by comparing the timing asymmetries between two identical wires, which caused by the capacitance of the attached probe, and its hardware overhead and analysis time are linearly proportional to the increment of the number of wires to protect. In this paper, we propose a compact probing detector with fast analysis time against invasive attacks. The proposed method can also provide the tunable detection capability by adjusting the minimum detectable capacitance in order to counteract the latest available probes which can support the lower input capacitance.
{"title":"Tunable Compact Probing Detector with Fast Analysis Time Against Invasive Attacks","authors":"Young-woo Lee, Youngkwang Lee, Minho Moon, Sungho Kang","doi":"10.1109/ISOCC47750.2019.9078494","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078494","url":null,"abstract":"The security-related information can be easily leaked by the invasive attacks including micro-probing, which can be potential threats. To prevent the targeted critical information from being leaked by the probe attempt, the secure shield as a protective layer is used on the topmost metal layer. The countermeasure method for detecting the micro-probing is usually conducted by comparing the timing asymmetries between two identical wires, which caused by the capacitance of the attached probe, and its hardware overhead and analysis time are linearly proportional to the increment of the number of wires to protect. In this paper, we propose a compact probing detector with fast analysis time against invasive attacks. The proposed method can also provide the tunable detection capability by adjusting the minimum detectable capacitance in order to counteract the latest available probes which can support the lower input capacitance.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126089846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-06DOI: 10.1109/ISOCC47750.2019.9078519
Kyung-Sub Son, Namyong Kim, Jin-Ku Kang
Abstract— An eye-open monitoring system based on signal counting is introduced. Data is sampled 2048 times and "0" or "1" is counted to determine eye-opening at each sampling point. The FPGA stores the counter value and outputs the estimated eye-diagram. Through the estimated eye-opening information, the eye calculates the open area and the optimal sampling point. The size and phase of the sampling point are controlled by 5-bit, respectively. The proposed eye-open monitor was fabricated through a 180-nm CMOS process and consumes 86mW at a 2Gb/s data rate, 1.8V supply.
{"title":"Counter-based Eye-open Monitoring System Design for High-speed Serial Interface","authors":"Kyung-Sub Son, Namyong Kim, Jin-Ku Kang","doi":"10.1109/ISOCC47750.2019.9078519","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078519","url":null,"abstract":"Abstract— An eye-open monitoring system based on signal counting is introduced. Data is sampled 2048 times and \"0\" or \"1\" is counted to determine eye-opening at each sampling point. The FPGA stores the counter value and outputs the estimated eye-diagram. Through the estimated eye-opening information, the eye calculates the open area and the optimal sampling point. The size and phase of the sampling point are controlled by 5-bit, respectively. The proposed eye-open monitor was fabricated through a 180-nm CMOS process and consumes 86mW at a 2Gb/s data rate, 1.8V supply.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"394 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126971267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-06DOI: 10.1109/ISOCC47750.2019.9078529
H. Sekiya, Y. Ozawa, Xiuqin Wei
This paper proposes a load-independent parallel resonant inverter. The proposed inverter can always maintain the constant-output voltage and the zero-current switching at turn-off instant against load variations. The fundamental characteristic was shown and confirmed from the experimental verifications.
{"title":"Load Independent Parallel Resonant Inverter","authors":"H. Sekiya, Y. Ozawa, Xiuqin Wei","doi":"10.1109/ISOCC47750.2019.9078529","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078529","url":null,"abstract":"This paper proposes a load-independent parallel resonant inverter. The proposed inverter can always maintain the constant-output voltage and the zero-current switching at turn-off instant against load variations. The fundamental characteristic was shown and confirmed from the experimental verifications.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128129496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-06DOI: 10.1109/ISOCC47750.2019.9078465
Seo Lin Jeong, Seung Yong Kim, J. Bae, M. Sunwoo
SC and SCL are the decoding algorithms for polar codes that have the disadvantage of high latency due to serial operations. Several algorithms, such as Fast-SSC, multibit decision, have been proposed to improve the latency with additional circuits, however, areas become larger. This paper proposes an efficient multibit decision algorithm to improve latency based on the SCL algorithm. In addition, we propose the combined nodes that combine node types of the fast-SSC algorithm to increase area efficiency and reduce the number of decoding cycles.
{"title":"Fast Multibit Decision Method for Successive-Cancellation List Polar Decoder","authors":"Seo Lin Jeong, Seung Yong Kim, J. Bae, M. Sunwoo","doi":"10.1109/ISOCC47750.2019.9078465","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078465","url":null,"abstract":"SC and SCL are the decoding algorithms for polar codes that have the disadvantage of high latency due to serial operations. Several algorithms, such as Fast-SSC, multibit decision, have been proposed to improve the latency with additional circuits, however, areas become larger. This paper proposes an efficient multibit decision algorithm to improve latency based on the SCL algorithm. In addition, we propose the combined nodes that combine node types of the fast-SSC algorithm to increase area efficiency and reduce the number of decoding cycles.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"140 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128161539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-06DOI: 10.1109/ISOCC47750.2019.9078500
Cheol-Won Jo, Kwang-yeob Lee
In this paper, MAC computation, which is the most used operation in neural network computing, is accelerated by multicycle_path. When using a pipeline, we can not divide the operation into fixed delays. Thus, exiting pipelines determine the operating frequency with the lowest frequency. We proposed the method confirmed that confirmed that the operation frequency of the whole process is improved by using multicycle_path to divide the operation into a certain delay and to perform the operation. In this paper, the experiment was divided into SingleCycle, Conventional Multicycle, MultiCycle_Ex and MultiCycle_Slice. Conventional Multicycle achieved 2.23 times higher operating frequency than SingleCycle, but resource usage tripled. MultiCycle_Ex achieved a 2.67 times higher operating frequency while maintaining the resource usage of SingleCycle, and MultiCycle_Slice achieved operating frequency about 8.2 times higher than SingleCycle.
{"title":"Design of multicycle path accelerator for neural network","authors":"Cheol-Won Jo, Kwang-yeob Lee","doi":"10.1109/ISOCC47750.2019.9078500","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078500","url":null,"abstract":"In this paper, MAC computation, which is the most used operation in neural network computing, is accelerated by multicycle_path. When using a pipeline, we can not divide the operation into fixed delays. Thus, exiting pipelines determine the operating frequency with the lowest frequency. We proposed the method confirmed that confirmed that the operation frequency of the whole process is improved by using multicycle_path to divide the operation into a certain delay and to perform the operation. In this paper, the experiment was divided into SingleCycle, Conventional Multicycle, MultiCycle_Ex and MultiCycle_Slice. Conventional Multicycle achieved 2.23 times higher operating frequency than SingleCycle, but resource usage tripled. MultiCycle_Ex achieved a 2.67 times higher operating frequency while maintaining the resource usage of SingleCycle, and MultiCycle_Slice achieved operating frequency about 8.2 times higher than SingleCycle.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134508267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-06DOI: 10.1109/ISOCC47750.2019.9078507
Chaeun Lee, Jaehyun Kim, Kiyoung Choi
Spiking neural networks (SNNs) are promising because they have the ability to represent signal strength information with a simple sequence of spikes having the same height. In this paper, we propose an RRAM-based analog neuron circuit for the weighted spiking neural network which is energy-efficient and hardware-friendly. We have designed the neuron circuit to show that the weighted spiking neural network can be implemented in analog and works properly.
{"title":"An RRAM-based Analog Neuron Design for the Weighted Spiking Neural network","authors":"Chaeun Lee, Jaehyun Kim, Kiyoung Choi","doi":"10.1109/ISOCC47750.2019.9078507","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078507","url":null,"abstract":"Spiking neural networks (SNNs) are promising because they have the ability to represent signal strength information with a simple sequence of spikes having the same height. In this paper, we propose an RRAM-based analog neuron circuit for the weighted spiking neural network which is energy-efficient and hardware-friendly. We have designed the neuron circuit to show that the weighted spiking neural network can be implemented in analog and works properly.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114356189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-06DOI: 10.1109/ISOCC47750.2019.9078495
Fabian Schuiki, Michael Schaffner, L. Benini
In this work we present the first complete design, silicon implementation and measurements in 22 nm FD-SOI of the Network Training Accelerator (NTX) architectural concept [1]. NTX is based on a newly designed partial carrysave "wide-inside" (300 bit) fused multiply-accumulate (FMAC) unit ensuring IEEE 754 compliance and a Root Mean Squared Error 1.7_lower than a conventional 32 bit FPU on long accumulations such as dot products and convolutions.
{"title":"NTX: A 260 Gflop/sW Streaming Accelerator for Oblivious Floating-Point Algorithms in 22 nm FD-SOI","authors":"Fabian Schuiki, Michael Schaffner, L. Benini","doi":"10.1109/ISOCC47750.2019.9078495","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078495","url":null,"abstract":"In this work we present the first complete design, silicon implementation and measurements in 22 nm FD-SOI of the Network Training Accelerator (NTX) architectural concept [1]. NTX is based on a newly designed partial carrysave \"wide-inside\" (300 bit) fused multiply-accumulate (FMAC) unit ensuring IEEE 754 compliance and a Root Mean Squared Error 1.7_lower than a conventional 32 bit FPU on long accumulations such as dot products and convolutions.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114792688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-06DOI: 10.1109/ISOCC47750.2019.9078466
T. Tan, Yujin Hyun, Jisu Kim, D. Choi, Hanho Lee
This paper presents a novel method to implement ring learning with errors (ring-LWE) cryptography for video-based face encryption and decryption on a graphics processing unit (GPU). By conducting ring arithmetic operations in parallel on a GPU, the processing time of these operations is significantly reduced. Consequently, ring-LWE encryption and decryption operations are remarkably improved. The simulation results conducted on GPU and CPU platforms using CUDA C++ show that the ring-LWE based face encryption and decryption operations implemented on a GPU are approximately 100 times faster than that implemented on a CPU.
{"title":"Ring-LWE Based Face Encryption and Decryption System on a GPU","authors":"T. Tan, Yujin Hyun, Jisu Kim, D. Choi, Hanho Lee","doi":"10.1109/ISOCC47750.2019.9078466","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078466","url":null,"abstract":"This paper presents a novel method to implement ring learning with errors (ring-LWE) cryptography for video-based face encryption and decryption on a graphics processing unit (GPU). By conducting ring arithmetic operations in parallel on a GPU, the processing time of these operations is significantly reduced. Consequently, ring-LWE encryption and decryption operations are remarkably improved. The simulation results conducted on GPU and CPU platforms using CUDA C++ show that the ring-LWE based face encryption and decryption operations implemented on a GPU are approximately 100 times faster than that implemented on a CPU.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124869543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-06DOI: 10.1109/ISOCC47750.2019.9078508
Young Hyun Yoon, S. Jang, Do Young Choi, Seung Eun Lee
In this paper, we propose a flexible embedded artificial intelligence (AI) system with high-speed neuromorphic controller. With the designed neuromorphic controller, the system receives data in high-speed and makes the neuro-processors to process the received data in parallel, efficiently. Also, the embedded system operates with the variable number of the neuro-processors that are available to apply in the various embedded systems. The neuromorphic controller was demonstrated with the field programmable gate array (FPGA) and we verified the feasibility of the entire system with the proposed controller.
{"title":"Flexible Embedded AI System with High-speed Neuromorphic Controller","authors":"Young Hyun Yoon, S. Jang, Do Young Choi, Seung Eun Lee","doi":"10.1109/ISOCC47750.2019.9078508","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078508","url":null,"abstract":"In this paper, we propose a flexible embedded artificial intelligence (AI) system with high-speed neuromorphic controller. With the designed neuromorphic controller, the system receives data in high-speed and makes the neuro-processors to process the received data in parallel, efficiently. Also, the embedded system operates with the variable number of the neuro-processors that are available to apply in the various embedded systems. The neuromorphic controller was demonstrated with the field programmable gate array (FPGA) and we verified the feasibility of the entire system with the proposed controller.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131344312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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