A Low-Power 20 Gbps Multi-phase MDLL-based Digital CDR with Receiver Equalization

2019 International SoC Design Conference (ISOCC) Pub Date : 2019-10-06 DOI:10.1109/ISOCC47750.2019.9078536

Heejae Hwang, Jongsun Kim

引用次数: 1

Abstract

A low-power 20 Gbps multi-phase multiplying delaylocked loop (MDLL)-based clock and data recovery (CDR) with receiver equalization is presented. The proposed MDLL-based digital CDR uses 2x-oversampling technique to lower the bit error rate (BER) and achieves fast lock time using an initial tracking mode. A multi-phase MDLL is utilized to provide the 8- phase reference clocks needed for the PI-based CDR, thereby achieving the power reduction effect. A near-ground signaling (NGS) receiver with a passive CTLE is used for lower power operation at 20 Gbps/channel. The proposed 20 Gbps CDR with receiver equalization is implemented in a 40nm CMOS process, achieving a power consumption of only 25.0 mW (=1.25 mW/Gb/s).

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基于接收机均衡的低功耗20gbps多相mdl数字话单

提出了一种基于低功耗20 Gbps多相乘法延迟锁环(MDLL)的时钟和数据恢复(CDR)接收机均衡器。本文提出的基于mdl的数字话单采用2倍过采样技术降低误码率，并采用初始跟踪模式实现快速锁定时间。多相MDLL用于提供基于pi的CDR所需的8相参考时钟，从而达到降低功耗的效果。具有无源CTLE的近地信号(NGS)接收器用于20 Gbps/信道的低功率操作。所提出的带有接收器均衡的20 Gbps CDR在40nm CMOS工艺中实现，功耗仅为25.0 mW (=1.25 mW/Gb/s)。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2019 International SoC Design Conference (ISOCC)

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