Y. Okuno, M. Okabe, T. Arakawa, I. Tomioka, T. Ohno, T. Noda, Y. Kuramitsu
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引用次数: 2
Abstract
Column macro-cell architecture has been verified to be advantageous for increasing silicon utilization in experimental circuit layouts. As an application, a 64-b multiplier with 32-kb RAM and 65-kb ROM using a 1.4-M transistor sea of gates (SOG) has been developed, using 0.8-μm two-layer-metal CMOS. Gate density of 1.5 kg/mm2 and bit densities of 1.9 kb/mm2 for RAM and 6.3/mm2 for ROM have been achieved
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