Strained Si/SiGe technology: status and opportunities

Abstract

Fabrication of sub-100 nm strained Si/SiGe MOSFETs using CMOS technology have been demonstrated, with current drives enhancements in both NFET and PFET. Material properties of strained Si and SiGe require careful modifications in CMOS process flow. Band offset induced shift in threshold voltages need to be compensated by device design and the difference in dopant diffusion properties also need to be taken into account. SGOI substrates can be fabricated by SIMOX, thermal diffusion of Ge and layer transfer techniques.