1.5 GHz OPAMP in 120nm digital CMOS

Franz Schlögl, H. Zimmermann
{"title":"1.5 GHz OPAMP in 120nm digital CMOS","authors":"Franz Schlögl, H. Zimmermann","doi":"10.1109/ESSCIR.2004.1356662","DOIUrl":null,"url":null,"abstract":"A high-speed operational amplifier, employing only regular-threshold devices in a 120 nm digital CMOS technology, with a two-signal-path topology, is presented. A single-stage high-frequency path allows a transit frequency of 1.5 GHz and a two-stage low-frequency path increases the DC gain to 40 dB. A new near-rail-to-rail class AB output stage is achieved with two local common-mode feedback loops.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"20","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 30th European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIR.2004.1356662","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 20

Abstract

A high-speed operational amplifier, employing only regular-threshold devices in a 120 nm digital CMOS technology, with a two-signal-path topology, is presented. A single-stage high-frequency path allows a transit frequency of 1.5 GHz and a two-stage low-frequency path increases the DC gain to 40 dB. A new near-rail-to-rail class AB output stage is achieved with two local common-mode feedback loops.
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1.5 GHz OPAMP在120nm数字CMOS
提出了一种仅采用常规阈值器件的高速运算放大器,采用120纳米数字CMOS技术,具有双信号路径拓扑结构。单级高频路径允许1.5 GHz的传输频率,两级低频路径将直流增益增加到40 dB。一个新的近轨到轨级AB输出阶段实现了两个本地共模反馈回路。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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