A Design Method of High Parallelism QC-LDPC Decoder Based on FPGA

Abstract

QC-LDPC(Quasi-Cyclic LDPC) is widely used in deep space communications due to its superior performance. Overlapped-NMSA(Normalization Min-Sum Algorithm) has similar error correction performance to NMSA, and it takes less time to complete an iteration process, so it is more suitable for the design and implementation of high-speed decoder. In this paper, an efficient storage addressing scheme suitable for high parallelism decoder is proposed, and the overall architecture of decoder is designed based on the storage addressing scheme. After the design of the decoder is completed, VIVADO and MATLAB simulation tests show that the decoder can run with a maximum clock frequency of 210MHz and a minimum throughput of about 1.1Gbps.