A variation tolerant architecture for ultra low power multi-processor cluster

Abstract

Process and environmental temperature variations have a detrimental effect on performance and reliability of modern embedded systems. This sensitivity to operating conditions significantly increases in ultra-low-power (ULP) devices and in all those applications that rely on reduced supply voltage to achieve energy efficiency. We propose a lightweight runtime solution to tolerate process and environmental temperature variations. The novelty of our solution is the ability to tackle both hold time and setup time sensitivity to variations by dynamically adapting latencies of the datapaths without compromising execution correctness. We extensively tested our solution evaluating the trade-offs, demonstrating the cost, performance, reliability gain compared to state-of-the-art static solutions. The proposed solution is able to reach a performance gain up to 30% with a very low (≈ 4%) area overhead.