{"title":"Modified transmission line pulse system and transistor test structures for the study of ESD","authors":"R. Ashton","doi":"10.1109/ICMTS.1995.513959","DOIUrl":null,"url":null,"abstract":"A modified Transmission Line Pulsing System for characterizing transistors under high currents for ESD performance prediction and understanding is presented which can both stress devices and measure damage. Guidelines for transistor test structure design for use with the system are presented and demonstrated for PMOS transistors.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"150 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings International Conference on Microelectronic Test Structures","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMTS.1995.513959","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 15
Abstract
A modified Transmission Line Pulsing System for characterizing transistors under high currents for ESD performance prediction and understanding is presented which can both stress devices and measure damage. Guidelines for transistor test structure design for use with the system are presented and demonstrated for PMOS transistors.
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