Horng-Yuan Shih, Wei-Hsien Chen, K. Juang, Tzu-Yi Yang, C. Kuo
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引用次数: 2
Abstract
An interference-sturdiness receiver with a current-mode filter for 3-5 GHz UWB applications is implemented in a 1.2V 0.13 mum CMOS process. The chip provides a maximum voltage gain of 70 dB and a dynamic range of 60 dB. The measured in-band OIP3 is +9.39 dBm, out-of-band IIP3 -15 dBm and noise figure 6.8 dB in the maximum gain mode. An algorithm for the automatic digital DC offset calibration is also demonstrated.
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