Analysis of traps-related effects hindering GFETs performance

Abstract

The effect of traps on DC and high-frequency behavior of a short channel single-layer graphene field-effect transistor (GFET) is discussed thoroughly in the present work. Trap-induced hysteresis is evident when a standard staircase measurement technique is applied while it is diminished when an opposing-pulse method is used. In both cases, forward and backward gate voltage (VGS) sweeps are utilized. A recently proposed analytical compact model accounting for traps activated both by vertical electric field and high-lateral electric field enabled by hot carriers, is accurately validated with both trap-affected and trap-reduced data. Important high-frequency figures of merit (FoM) such as cut-off and maximum oscillation frequencies as well as the intrinsic gain of the GFET under test, are also derived from the model, and exhibit a strong trap dependence through the DC operating point of the device. These FoM not only demonstrate VGS shifts, but also, they exhibit magnitude alterations due to traps impact even when the Dirac voltage of the GFET under test coincides in both forward and backward staircase measurement schemes.