An XML Schema for Representing Reusable IP Cores for Reconfigurable Computing

Abstract

The reuse of intellectual property (IP) cores within reconfigurable computing systems is a promising approach for improving the productivity of reconfigurable system design. Further, there are a large variety of reusable IP cores available for a variety of application-specific functions. These cores, however, are created from different design tools and are difficult to integrate into a single reconfigurable system design. To facilitate the reuse of these cores, an XML schema has been created for representing the essential details of a core in a reconfigurable computing design environment. This paper presents this XML schema and describes how it can be used to facilitate reuse in reconfigurable computing systems.