{"title":"A low-area digitalized channel selection filter for DSRC system","authors":"Hung-Wen Lin, Jin-Yi Lin, Min-Tai Chuang","doi":"10.1109/VLSI-DAT.2014.6834882","DOIUrl":null,"url":null,"abstract":"This paper proposes a low-area digitalized band-pass filter (BPF) for the DSRC Receiver. The resonance of active inductor and MOS varactor are utilized to generate band-pass filtering characteristics. To apply for different passband, both the inductance of the inductor and the capacitance of the varctor are designed to be adjusted via digital controls. Band selectivity is raised by cascading stages of BPF cell. In 0.18um CMOS technology, a 7bits 6-stage BPF template occupies an active area of 0.16mm2 and consumes a power of 14.8mW under 1.8V of supplies. The center frequency is ranged form 27MHz to 41MHz with an average frequency resolution of 0.11MHz and the adjacent channel suppression is -16dB@ 40±2.5MHz. The input third-order intercept point is 6dbm.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-DAT.2014.6834882","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
This paper proposes a low-area digitalized band-pass filter (BPF) for the DSRC Receiver. The resonance of active inductor and MOS varactor are utilized to generate band-pass filtering characteristics. To apply for different passband, both the inductance of the inductor and the capacitance of the varctor are designed to be adjusted via digital controls. Band selectivity is raised by cascading stages of BPF cell. In 0.18um CMOS technology, a 7bits 6-stage BPF template occupies an active area of 0.16mm2 and consumes a power of 14.8mW under 1.8V of supplies. The center frequency is ranged form 27MHz to 41MHz with an average frequency resolution of 0.11MHz and the adjacent channel suppression is -16dB@ 40±2.5MHz. The input third-order intercept point is 6dbm.
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