Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7047092
A. Oates
Summary form only given. Moore's law continues to the engine of growth for the global electronics industry. The understanding of IC degradation mechanisms has resulted in rapid reliability improvements that have enabled the rapid rate technology progression we have experienced. Going forward it is clear that the reliability margins the industry has enjoyed in the past will shrink. The question is now whether reliability will pose a constraint on Moore's law. In this talk we will discuss reliability issues that can most directly impact the industry's capability to maintain the pace of technology progression required by Moore's law.
{"title":"Will reliability limit Moore's law?","authors":"A. Oates","doi":"10.1109/IEDM.2014.7047092","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047092","url":null,"abstract":"Summary form only given. Moore's law continues to the engine of growth for the global electronics industry. The understanding of IC degradation mechanisms has resulted in rapid reliability improvements that have enabled the rapid rate technology progression we have experienced. Going forward it is clear that the reliability margins the industry has enjoyed in the past will shrink. The question is now whether reliability will pose a constraint on Moore's law. In this talk we will discuss reliability issues that can most directly impact the industry's capability to maintain the pace of technology progression required by Moore's law.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122635854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-16DOI: 10.1109/VLSI-DAT.2014.6834921
Chia-I Chen, Chin-Yeh Yu, Yen-Ju Lu, Chi-Feng Wu
For decades, several researchers in both academic and industrial dedicate to reduce the widen gap between technology capabilities and productivity of hardware designer. HLS (high-level synthesis) is one of the promising possibilities to speed up the product development time. In this paper, we propose a HLS framework. Then design and verify an FPU (floating-point unit) via the proposed framework. The target design goes through the entire flow from a behavioral model down to gate-level netlist. Discussion on general issues of HLS is provided as experience sharing. QoR (quality-of-result) of the framework and the FPU are also evaluated at the end of this article.
{"title":"Apply high-level synthesis design and verification methodology on floating-point unit implementation","authors":"Chia-I Chen, Chin-Yeh Yu, Yen-Ju Lu, Chi-Feng Wu","doi":"10.1109/VLSI-DAT.2014.6834921","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834921","url":null,"abstract":"For decades, several researchers in both academic and industrial dedicate to reduce the widen gap between technology capabilities and productivity of hardware designer. HLS (high-level synthesis) is one of the promising possibilities to speed up the product development time. In this paper, we propose a HLS framework. Then design and verify an FPU (floating-point unit) via the proposed framework. The target design goes through the entire flow from a behavioral model down to gate-level netlist. Discussion on general issues of HLS is provided as experience sharing. QoR (quality-of-result) of the framework and the FPU are also evaluated at the end of this article.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121369481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834872
Po-Han Wang, Gen-Hong Liu, J. Yeh, Tse-Min Chen, Hsu-Yao Huang, Chia-Lin Yang, Siyi Liu, James Greensky
The integrated CPU/GPU architecture brings performance advantage since the communication cost between the CPU and GPU is reduced, and also imposes new challenges in processor architecture design, especially in the management of shared memory resources, e.g, the last-level cache and memory bandwidth. Therefore, a micro-architecture level simulator is essential to facilitate researches in this direction. In this paper, we develop the first cycle-level full-system simulation framework for CPU-GPU integration with detailed memory models. With the simulation framework, we analyze the communication cost between the CPU and GPU for GPU workloads, and perform memory system characterization running both applications concurrently.
{"title":"Full system simulation framework for integrated CPU/GPU architecture","authors":"Po-Han Wang, Gen-Hong Liu, J. Yeh, Tse-Min Chen, Hsu-Yao Huang, Chia-Lin Yang, Siyi Liu, James Greensky","doi":"10.1109/VLSI-DAT.2014.6834872","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834872","url":null,"abstract":"The integrated CPU/GPU architecture brings performance advantage since the communication cost between the CPU and GPU is reduced, and also imposes new challenges in processor architecture design, especially in the management of shared memory resources, e.g, the last-level cache and memory bandwidth. Therefore, a micro-architecture level simulator is essential to facilitate researches in this direction. In this paper, we develop the first cycle-level full-system simulation framework for CPU-GPU integration with detailed memory models. With the simulation framework, we analyze the communication cost between the CPU and GPU for GPU workloads, and perform memory system characterization running both applications concurrently.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124439920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834904
Y. Yu, Fujun Huang, Chorng-Kuang Wang
This work verifies the technique - Master-Slave digital to analog converter (M-S DAC) - for reducing the significant energy dissipation of 93% in comparison with the conventional capacitor array in successive approximation register analog to digital converter (SAR ADC). This technique avoiding the redundant charge and discharge in larger capacitors is demonstrated by a fabricated chip in 180nm CMOS standard process, and reaches performance including signal-to-noise-and-distortion ratio of 59.2dB in equivalent 9.6-bit, power consumption of 28 μW at the sampling frequency of 500KS/s with the conditions of supplying voltage of 1V in core area of 0.15mm2.
{"title":"A 1V 10-bit 500KS/s energy-efficient SAR ADC using Master-Slave DAC technique in 180nm CMOS","authors":"Y. Yu, Fujun Huang, Chorng-Kuang Wang","doi":"10.1109/VLSI-DAT.2014.6834904","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834904","url":null,"abstract":"This work verifies the technique - Master-Slave digital to analog converter (M-S DAC) - for reducing the significant energy dissipation of 93% in comparison with the conventional capacitor array in successive approximation register analog to digital converter (SAR ADC). This technique avoiding the redundant charge and discharge in larger capacitors is demonstrated by a fabricated chip in 180nm CMOS standard process, and reaches performance including signal-to-noise-and-distortion ratio of 59.2dB in equivalent 9.6-bit, power consumption of 28 μW at the sampling frequency of 500KS/s with the conditions of supplying voltage of 1V in core area of 0.15mm2.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124915079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834918
S. Goel, Min-Jer Wang, S. Adham, Ashok Mehta, F. Lee
To meet power, performance and area requirements of modern electronic products, heterogeneous system integration where dies implemented in dedicated, optimized process technologies are stacked together to form a system is inevitable. The use of known-good pre-fabricated dies provides substantial reduction in time-to-market for integrated products. However, as dies from different suppliers using different technologies are used, finding source of design errors or manufacturing defects becomes very challenging if an integrated system fails in production. The system integrator has the onus to include test and diagnosis features that can enable post-silicon debugging. In this paper, we present a silicon diagnosis case study for a TSMC CoWoSTM based heterogeneous 3D chip. We demonstrate how the Design-for-Diagnosis features implemented on the logic die were used to isolate interconnects testing failures. We were not only able to speed up the diagnosis but also able to find the real source of failure, which was a design and modeling issue in one of the 3rd party known-good-die.
{"title":"Design-for-diagnosis: Your safety net in catching design errors in known good dies in CoWoSTM/3D ICs","authors":"S. Goel, Min-Jer Wang, S. Adham, Ashok Mehta, F. Lee","doi":"10.1109/VLSI-DAT.2014.6834918","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834918","url":null,"abstract":"To meet power, performance and area requirements of modern electronic products, heterogeneous system integration where dies implemented in dedicated, optimized process technologies are stacked together to form a system is inevitable. The use of known-good pre-fabricated dies provides substantial reduction in time-to-market for integrated products. However, as dies from different suppliers using different technologies are used, finding source of design errors or manufacturing defects becomes very challenging if an integrated system fails in production. The system integrator has the onus to include test and diagnosis features that can enable post-silicon debugging. In this paper, we present a silicon diagnosis case study for a TSMC CoWoSTM based heterogeneous 3D chip. We demonstrate how the Design-for-Diagnosis features implemented on the logic die were used to isolate interconnects testing failures. We were not only able to speed up the diagnosis but also able to find the real source of failure, which was a design and modeling issue in one of the 3rd party known-good-die.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122561645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834884
Shang-Yi Chuang, Jia-Ju Liao, Chia-Ching Chou, Chia-Chi Chang, W. Fang
This study proposed an effective signal processing system based on Ensemble Empirical Mode Decomposition (EEMD) method for the analysis of arterial blood pressure (ABP). The whole system was implemented on an ARM-based SoC development platform to attain the on-line non-stationary signal processing. A non-invasive blood pressure acquisition device (NIBP100D) was used to record the continuous ABP as the input signal. According to the non-stationary characteristics of ABP, EEMD is useful to achieve accurate decomposition for ABP spectral analysis. The signal was decomposed into several Intrinsic Mode Functions (IMFs) by EEMD, and quantitatively assessed by fast Fourier transform (FFT). The results showed that the proposed EEMD processor can effectively solve the mode mixing problem of Empirical Mode Decomposition (EMD) and the FFT spectrum of IMF5, IMF6, and IMF7 to reveal heart rate and respiration.
{"title":"An effective arterial blood pressure signal processing system based on EEMD method","authors":"Shang-Yi Chuang, Jia-Ju Liao, Chia-Ching Chou, Chia-Chi Chang, W. Fang","doi":"10.1109/VLSI-DAT.2014.6834884","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834884","url":null,"abstract":"This study proposed an effective signal processing system based on Ensemble Empirical Mode Decomposition (EEMD) method for the analysis of arterial blood pressure (ABP). The whole system was implemented on an ARM-based SoC development platform to attain the on-line non-stationary signal processing. A non-invasive blood pressure acquisition device (NIBP100D) was used to record the continuous ABP as the input signal. According to the non-stationary characteristics of ABP, EEMD is useful to achieve accurate decomposition for ABP spectral analysis. The signal was decomposed into several Intrinsic Mode Functions (IMFs) by EEMD, and quantitatively assessed by fast Fourier transform (FFT). The results showed that the proposed EEMD processor can effectively solve the mode mixing problem of Empirical Mode Decomposition (EMD) and the FFT spectrum of IMF5, IMF6, and IMF7 to reveal heart rate and respiration.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130517759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834915
Bumman Kim
Summary form only given. The CMOS PA becomes a reality due to the active research work in recent years. But the performance is not up to the expectation because of the inherent problems of CMOS such as low power density and poor linearity. To enhance the performance further, various adaptation techniques are applied to CMOS PA, i. e. at the gate and drain. In this talk, we will introduce the advanced CMOS PA with the adaptaions.
{"title":"Bias adapted operation of CMOS PA for handset application","authors":"Bumman Kim","doi":"10.1109/VLSI-DAT.2014.6834915","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834915","url":null,"abstract":"Summary form only given. The CMOS PA becomes a reality due to the active research work in recent years. But the performance is not up to the expectation because of the inherent problems of CMOS such as low power density and poor linearity. To enhance the performance further, various adaptation techniques are applied to CMOS PA, i. e. at the gate and drain. In this talk, we will introduce the advanced CMOS PA with the adaptaions.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127696284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834899
Shen-Fu Hsiao, Wen-Ling Wang, Po-Sheng Wu
Dynamic Programming (DP)-based stereo matching consists of three major parts: matching cost computation (M.C.C.), minimum cost accumulation (M.C.A.), and disparity optimization (D.O.). This paper presents two architectures of implementations: array-based and memory-based. The array-based implementation is a systolic-like design consisting of regularly connected processing elements (PEs). The memory-based design replaces most of the PEs by memory units in order to reduce area cost. Both architectures adopt the concept of double buffer designs in order to process contiguous images. Experimental results show that the proposed design can achieve real-time processing speed at reasonable area cost.
{"title":"VLSI implementations of stereo matching using Dynamic Programming","authors":"Shen-Fu Hsiao, Wen-Ling Wang, Po-Sheng Wu","doi":"10.1109/VLSI-DAT.2014.6834899","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834899","url":null,"abstract":"Dynamic Programming (DP)-based stereo matching consists of three major parts: matching cost computation (M.C.C.), minimum cost accumulation (M.C.A.), and disparity optimization (D.O.). This paper presents two architectures of implementations: array-based and memory-based. The array-based implementation is a systolic-like design consisting of regularly connected processing elements (PEs). The memory-based design replaces most of the PEs by memory units in order to reduce area cost. Both architectures adopt the concept of double buffer designs in order to process contiguous images. Experimental results show that the proposed design can achieve real-time processing speed at reasonable area cost.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"8 Pt 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126272628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834873
Yi-Ming Wang, M. Chao, Shi-Hao Chen, Hung-Chun Li
This paper presents a switch-routing framework which can generate a feasible Hamiltonian-path switch routing while minimizing the dynamic IR drop of a targeted fragile active domain with an analytical model. The accuracy of the analytical model and the effectiveness of the proposed framework are validated through an advanced multi-domain mobile-phone MTCMOS design.
{"title":"Power-switch routing for reducing dynamic IR drop in multi-domain MTCMOS designs","authors":"Yi-Ming Wang, M. Chao, Shi-Hao Chen, Hung-Chun Li","doi":"10.1109/VLSI-DAT.2014.6834873","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834873","url":null,"abstract":"This paper presents a switch-routing framework which can generate a feasible Hamiltonian-path switch routing while minimizing the dynamic IR drop of a targeted fragile active domain with an analytical model. The accuracy of the analytical model and the effectiveness of the proposed framework are validated through an advanced multi-domain mobile-phone MTCMOS design.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131744192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834889
Joseph Sankman, Minkyu Song, D. Ma
Ever-increasing power demands of microprocessors have necessitated fast-response, high-speed power converters. This paper presents a fast transient, hysteretic current-mode converter design with a push-pull current pump. By using a current feedback technique in contrast with the parallel feedback control approaches by the prior art, performance and stability are greatly enhanced. The system is implemented and verified on a 0.18 μm CMOS process through fully transistor-level simulations, operating up to 40 MHz. In comparison with the buck converter by itself, the current pump improves the transient response by reducing VOUT undershoot magnitude and settling time by 33.3% and 25.6%, respectively, and overshoot magnitude and settling time by 18.3% and 40.4%, respectively. Undershoot and overshoot are maintained below 3%, at 2.8% and 2.9%, respectively.
{"title":"A 40-MHz current-mode hysteretic controlled switching converter with digital push-pull current pumping technique for high performance microprocessors","authors":"Joseph Sankman, Minkyu Song, D. Ma","doi":"10.1109/VLSI-DAT.2014.6834889","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834889","url":null,"abstract":"Ever-increasing power demands of microprocessors have necessitated fast-response, high-speed power converters. This paper presents a fast transient, hysteretic current-mode converter design with a push-pull current pump. By using a current feedback technique in contrast with the parallel feedback control approaches by the prior art, performance and stability are greatly enhanced. The system is implemented and verified on a 0.18 μm CMOS process through fully transistor-level simulations, operating up to 40 MHz. In comparison with the buck converter by itself, the current pump improves the transient response by reducing VOUT undershoot magnitude and settling time by 33.3% and 25.6%, respectively, and overshoot magnitude and settling time by 18.3% and 40.4%, respectively. Undershoot and overshoot are maintained below 3%, at 2.8% and 2.9%, respectively.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133519093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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